Abstract
Reasonable trade-off between the ASIC performance and GPP flexibility is the main objective of reconfigurable computing systems. Dynamic Reconfigurable computing platform using embedded just-in-time (JIT) compilation is the most flexible platform among others. All complex computing kernels can be translated to bitstream to be executed on FPGA using an embedded processor of dedicated specialized hardware. The main challenge in these systems is FPGA design automation time. Executing the CAD algorithms on embedded processor is too time-consuming and normally is not feasible for real applications. Placement is the most computative part of CAD algorithm. Therefore, a new FPGA placement algorithm is proposed in this paper which makes reasonable trade-off between execution time and quality of placement. The proposed algorithm includes two stages: force-directed placement and simulated annealing placement. The proposed algorithm is very low execution time to be useful in JIT compilation without considerable degradation on the quality of placement. Experimental results show $$2.33\times $$2.33A— speedup in execution time in cost of 3Â % overhead in channel tracks numbers.
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