Pixel Readout Chip Research Articles

First results on the final readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

The CMS Readout Chip (CROC) is a 65nm CMOS hybrid pixel readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker. The chip has been developed by the CERN RD53 Collaboration in order to withstand radiation doses up to 10MGy and hit rates up to 3GHzcm−2 on the innermost tracking layer. Moreover, it must handle an increased sensor granularity (pixel size of 2500µm2) with respect to current detectors and operate at detection thresholds as low as 1000e. Twenty wafers of the prototype chip (CROCv1) have been produced in 2021. The CROCv1 characterisation and verification campaign has, overall, demonstrated the radiation resistance of the chip and its performance. The production version of the chip (CROCv2) was submitted in October 2023 and the engineering run wafers have been received in January 2024. In this contribution, the first results from CROCv2 wafer-level testing of more than 1900 chips from the engineering run will be outlined.

A 14-Bit Digital to Analog Converter for a Topmetal-CEE Pixel Readout Chip

The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB.

RD53 pixel chips for the ATLAS and CMS Phase-2 upgrades at HL-LHC

The Phase-2 upgrades at the High-Luminosity LHC of ATLAS and CMS experiments at CERN will require a new tracker with readout electronics operating in extremely harsh radiation environment (1 Grad), high hit rate (3.5 GHz/cm2) and high data rate readout (5 Gb/s). The RD53 collaboration is a joint effort between the ATLAS and CMS to qualify the chosen 65 nm CMOS technology in high radiation environment and develop the pixel readout chips of both experiments. After a half-scale demonstrator (RD53A) and full scale prototypes of the two ASICs (RD53B-ATLAS and RD53B-CMS), largely used by the two communities to characterize 3D and planar sensors, RD53 developed and submitted to foundry in 2023 the production chips. A general overview of the chip architecture will be described.

First results from the RD53 ATLAS pixel production readout ASIC (ITkPixV2) for HL-LHC

The Phase-2 upgrades of ATLAS and CMS for the High-Luminosity LHC (HL-LHC), require a new tracker with robust readout electronics capable of withstanding extreme radiation (1 Grad), a high hit rate (3 GHz/cm2), and a high data rate readout (5 Gb/s). In a joint effort between ATLAS and CMS, pixel detector readout chips have been designed by the RD53 collaboration in 65 nm CMOS technology. Based on a half-sized demonstrator (RD53A), two chip variants were designed for ATLAS and CMS, respectively. The ATLAS pre-production readout chip, ITkPixV1, was characterised in detail, and informed by the results, the final ATLAS pixel readout chip, ITkPixV2, has been designed, submitted, and the first wafers were received in July 2023. This contribution provides an overview of the characterisation measurements performed on the ITkPixV2 chip so far, focusing on bench-top testing of chip functionality, and first results of X-ray irradiation studies to assess the radiation tolerance of the chip.

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

A 5.12-Gbps serializer circuit for front-end fast readout electronics of silicon pixelated detectors

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE.

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes.The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

High-rate, high-resolution single photon X-ray imaging: Medipix4, a large 4-side buttable pixel readout chip with high granularity and spectroscopic capabilities

The Medipix4 chip is the latest member in the Medipix/Timepix family of hybrid pixel detector chips aimed at high-rate spectroscopic X-ray imaging using high-Z materials. It can be tiled on all 4 sides making it ideal for constructing large-area detectors with minimal dead area. The chip is designed to read out a sensor of 320 × 320 pixels with dimensions of 75 μm× 75 μm or 160 × 160 pixels with dimensions of 150 μm× 150 μm. The readout architecture features energy binning of the single photons, which includes charge sharing correction for hits with energy spread over adjacent pixels. This paper presents the specifications, architecture, and circuit implementation of the chip, along with the first electrical measurements.

RD53B Wafer Testing for the ATLAS ITk Pixel Detector

RD53B/ITkPix-V1 is the most recent hybrid pixel readout chip development for the ATLAS pixel detector at the HL-LHC. It is the first full-scale 65 nm hybrid pixel-readout chip of its kind. ITkPix-V1 consists of more than one billion transistors with a high memory triplication ratio to cope with the high particle density at the heart of ATLAS. Chips will be as close to the interaction point as possible to optimize the resolution of impact parameters. The ITkPix-V1 chip features a 5-Gbit connection, with special data compression to deal with high hit intensities. In addition, a low-power, low-noise analog front-end is used to ensure high readout speeds and low detection thresholds. Failure of chips in ATLAS would be problematic. Therefore, a thorough test is necessary before and during production. For this purpose, the Bonn ATLAS group has developed BDAQ53, a fast and versatile simulation and testing environment that allows small and large-scale testing for ITkPix-V1 and its successor chips. This conference note will give an overview of the testing environment while focusing on large-scale wafer testing to evaluate ITkPix-V1’s suitability for its deployment at the HL-LHC.

A charge-integration pixel readout chip features IR-drop effect mitigation by distributed LDOs

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip, which is designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The targeting pixel array of a full-size chip is 128 × 128 with a pixel pitch of 100 μm. The dynamic range of HYLITE is 1 ∼ 10000 photons at 12 keV, and the frame rate is 10 kHz. Large array size, high dynamic range, and high readout speed result in a big challenge of large power consumption and a significant IR-Drop effect. We implemented HYLITE0.2, which is the second prototype chip fabricated in a CMOS 130 nm process. Compared with HYLITE0.1, HYLITE0.2 aims to implement a full-function chip with a further shrunk pixel size, while the foreseen problem of severe IR-Drop effect of the full-size chip must be solved. To mitigate the IR-Drop effect, we proposed a novel architecture of distributed in-array Low-Dropout Regulators (LDOs). The pixel array consists of 16 × 24 pixels, and the full functionality was implemented within a pixel pitch of 100 μm. Measurements show that pixels powered by the proposed architecture work well, and the gain gradient of those pixels is 31.8% of the pixels powered by the conventional architecture.

Characterization of a high bandwidth readout chain for the CMS phase-2 pixel upgrade

The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel readout chip will be controlled with a single serial input stream at 160 Mb/s and will send out data via four current mode logic (CML) 1.28 Gb/s outputs. The readout chips will be grouped in modules and connected with up to 1.6 meters long low-mass electrical links to Low-Power Gigabit Transceivers (lpGBT) and Versatile Link PLUS Transceiver (VTRx+) modules that send the data optically to off-detector electronics at 10 Gb/s. The characterization of these components and system tests of the readout chain are presented.

A prototype pixel readout chip working in single photon counting mode with a novel charge sharing suppression scheme

Spectral distortion due to the charge sharing effect becomes a severe issue in single-photon counting pixel detectors. The HEPS-BPIX4 prototype chip, dedicated for the HEPS in China, implements a novel architecture to mitigate charge sharing and permit spectroscopic imaging with high efficiency. In the architecture, a central pixel communicates with others in a cluster of 3 × 3 pixels. The algorithm simulation showed a charge sharing elimination accuracy better than 90%. The prototype chip has been designed in a 130 nm CMOS technology. The preliminary measurements show a charge gain of 48 mV/ke− and an equivalent noise charge of 150 e− rms. Detailed tests in a 4 × 4 pixel array for the charge sharing are performed using electrical test pulses. The hit allocation in the core four adjacent pixels of the array indicates that effective suppression of charge sharing has been realized.

Measurements of the radiation damage to the ITkPixV1 chip in X-ray irradiations

The upgrade of the ATLAS Inner Tracker (ITk) requires a pixel readout chip that can withstand the harsh environment of HL-LHC, with a peak luminosity of 5×1034cm−1s−1 and an estimated total ionising dose (TID) of around 1 Grad. The ITkPixV1 chip is the latest readout chip prototype for the ITk pixel upgrade. The radiation tolerance of this chip has been measured experimentally in irradiation campaigns using X-rays. The chip utilises a large number of digital cells in the chip logic, and the radiation damage to these cells is characterised by considering ring oscillator gate delays. The analog front-end is studied by tuning the chip thresholds before and after irradiation. Both the digital and analog logic show no operational issues after irradiation to 1 Grad (at a dose rate of 4 Mrad/h).

X-ray irradiation measurements of the radiation tolerance of the ITkPixV1 ATLAS pixel readout chip

The ITkPixV1 chip is the pre-production pixel readout chip for the Phase-2 Upgrade of the ATLAS experiment at the HL-LHC. The harsh environment of HL-LHC, including a peak luminosity of 5 × 1034 cm−1 s−1 and an estimated total ionising dose (TID) of around 1 Grad throughout its lifetime is placing strong requirements on the radiation tolerance of the chip. The radiation tolerance of the ITkPixV1 chip has been tested in irradiation campaigns using X-rays. The digital and analog front-end have been tested up to total doses of 1 Grad (at a dose rate of 4 Mrad/h) and show no significant operational issues.

The Selena Neutrino Experiment

Imaging sensors made from an ionization target layer of amorphous selenium (aSe) coupled to a silicon complementary metal-oxide-semiconductor (CMOS) active pixel array for charge readout are a promising technology for neutrino physics. The high spatial resolution in a solid-state target provides unparalleled rejection of backgrounds from natural radioactivity in the search for neutrinoless ββ decay and for solar neutrino spectroscopy with 82Se. We present results on the ionization response of aSe measured from the photoabsorption of 122 keV γ rays in a single-pixel device. We report on the progress in the fabrication and testing of the first prototype imaging sensors based on the Topmetal II − pixelated CMOS charge readout chip. We explore the scientific reach of a large neutrino detector with the proposed technology based on our experimental understanding of the sensor performance.

Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC

The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.

HEPS-BPIX3: a fine pitch pixel readout chip working in single photon counting mode for synchrotron radiation applications

HEPS-BPIX3 is a hybrid pixel detector readout chip for X-ray applications for the High Energy Photon Source (HEPS) in China. The readout chip contains an array of 88 × 88 pixels with a pixel size of 55 μm × 55 μm, working in single photon counting mode. Each pixel handles both polarities of positive and negative input charge signals and has a counting depth of 11 bits. Using a clock with a frequency up to 160 MHz, the chip can read out serially with zero dead time. Designed in a 130 nm CMOS technology, the chip has been measured and given the CSA charge gain of 17.6 mV/ke- for electron collection and 13 mV/ke- for hole collection, respectively. Bump-bonded detector modules with a 320-μm-thick silicon sensor were also tested. The test results showed an equivalent input noise of 156 e- and a counting rate up to 2.2 Mcps. Besides, an image using an X-ray tube was demonstrated and a frame rate of 1.8 kHz could be guaranteed. Measured characteristics present the normal functionality of the HEPS-BPIX3 chip and prove that the chip satisfies the HEPS requirements.

Vertically Integrated System with Microfabricated 3D Sensors and CO2 Microchannel Cooling

The growing demand for miniaturized radiation-tolerant detection systems with fast responses and high-power budgets has increased the necessity for smart and efficient cooling solutions. Several groups have been successfully implementing silicon microfabrication to process superficial microchannels to circulate coolants, in particular, in high-energy physics experiments, where the combination of low material budget to reduce noise generated by multiple scattering events and high radiation fluences is required. In this study, we report tests performed on an 885-µm–thick vertically integrated system. The system consists of a layer of microfabricated silicon channels for temperature management integrated to radiation-tolerant microfabricated 3D sensors, with electrodes penetrating perpendicularly to the silicon bulk, bump-bonded to an ATLAS FE-I4 pixel readout chip of 100 µm thickness, 2 × 2 cm2, and 26,880 pixels (each measuring 250 × 50 μm2). The system’s electrical and temperature characterization under CO2 cooling as well as the response to minimum ionizing particles from radioactive sources and particle beams before and after 2.8 ×1015 neq cm−2 proton irradiation will be discussed.

Design and Characterization of the CLICTD Pixelated Monolithic Sensor Chip

A novel monolithic pixelated sensor and readout chip, the compact linear collider tracker detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the compact linear collider (CLIC) and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of $16\times 128$ elongated channels, each measuring $300\times 30\,\,\mu \text {m}^{2}$ . Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit time-of-arrival (with 10 ns time bins) and 5-bit time-over-threshold measurement is performed on the combined digital output of the 8 subpixels in every channel. The chip has been fabricated in two process variants and characterized in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e− and a noise of about 14 e− rms. The design aspects and characterization results of the CLICTD chip are presented.

Radiation resistant innovative 3D pixel sensors for the CMS upgrade at the High Luminosity LHC

Results of an extensive R&D program aiming at radiation hard, small pitch, 3D pixel sensors are reported. The CMS experiment is supporting this R&D in the scope of the Inner Tracker upgrade for the High Luminosity phase of the CERN Large Hadron Collider (HL-LHC). In the HL-LHC the Inner Tracker will have to withstand an integrated fluence up to 2.3×1016neq/cm2. A small number of 3D sensors were interconnected with the RD53A readout chip, which is the first prototype of 65 nm CMOS pixel readout chip designed for the HL-LHC pixel trackers. In this paper results obtained in beam tests before and after irradiation are reported. The irradiation of a single chip module was performed up to a maximum equivalent fluence of about 1×1016neq/cm2. The analysis of the collected data shows excellent performance: the spatial resolution in not irradiated sensors can reach about 3 to 5 μm, for inclined tracks, depending on the pixel pitch. The measured hit detection efficiencies are close to 99% measured both before and after the above mentioned irradiation fluence.