Pixel Pad Research Articles

Development of novel single-die hybridisation processes for small-pitch pixel detectors

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution — an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55 µm pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the two interconnect processes and presents preliminary hybridisation results with CLICpix2 and Timepix3 sensors and ASICs.

Employing U-NET and Rotational Based Convolutional Neural Network to Build an Automatic Lung Cancer Segmentation and Classification System

The most common cancer-related cause of death globally is lung cancer. The key to effective lung cancer treatment and higher survival rates is early diagnosis. Converting a radiologist's diagnosing procedure to computer assisted results in more accurate results and an earlier diagnosis. The difficulty is that building an effective model for segmentation and classification. In this paper, we suggest a system for detecting lung cancer that makes use of a number of methods for precise and effective diagnosis. To enhance picture quality, our method pre-processes CT scan images using a Gaussian filter and contrast stretching. For the purpose of determining the borders of lung nodules with high precision, the U-Net architecture with the Adam optimizer is used. Then, a Gaussian mixture model (GMM) with EM optimisation and pixel padding is used to extract features. The rotational-based Convolutional Neural Network (RBCNN) classifier successfully categorises the nodules as benign and malignant using these form variables as inputs

Periodic wrappings in coded aperture imaging

We classify all coded masks onto which cyclic difference sets can be wrapped periodically using a generalization of the Finger and Prince construction. In particular, we establish simple numerical criteria which determine whether any given mask can be wrapped periodically in this way and, for each mask which can, we provide explicit constructions which will produce at least one such wrapping. We show that all periodic wrappings currently reported in the literature are special cases of our explicit constructions, and we often provide simpler alternatives. Using these constructions we show that all Singer cyclic difference sets of practical size and open fraction can be wrapped exactly onto masks which are very nearly as compact and symmetrical as hexagons, without the need for pixel padding.

Mask design and fabrication in coded aperture imaging

We introduce the new concept of a row-spaced mask, where a number of blank rows are interposed between every pair of adjacent rows of holes of a conventional cyclic difference set based coded mask. At the cost of a small loss in signal-to-noise ratio, this can substantially reduce the number of holes required to image extended sources, at the same time increasing mask strength uniformly across the aperture, as well as making the mask automatically self-supporting. We also show that the Finger and Prince construction can be used to wrap any cyclic difference set onto a two-dimensional mask, regardless of the number of its pixels. We use this construction to validate by means of numerical simulations not only the performance of row-spaced masks, but also the pixel padding technique introduced by in ’t Zand. Finally, we provide a computer program CDSGEN.EXE which, on a fast modern computer and for any Singer set of practical size and open fraction, generates the corresponding pattern of holes in seconds.

Qpix v.1: A high speed 400-pixels readout LSI with 10-bit 10MSps pixel ADCs

Abstract Qpix is a multi-functional CMOS pixel readout LSI, which can directly measure the total deposited charge, as well as time of flight (TOF) and time over threshold (TOT) in each pixel. Qpix v.1 is the newest version of Qpix. The chip is designed and fabricated in a six-metal 0.18 μ m commercial CMOS process. It has a dimension of 5 mm×5 mm and possesses 400 identical pixels each with an area of 200 μ m × 200 μ m . Except the 130 μ m × 140 μ m active circuitry, the pixel pad occupies almost all the other area. This large pixel pad in each pixel can be used as an active anode to directly collect the charges generated in the gas chamber such as a micro-pattern gas detector based time projection chamber. The successive approximation register ADC in each pixel is optimized to 10 bits and 10 MSps without any increase of area. Also, offset calibration technology is applied to both the amplifier and the comparators to reduce the mismatch between pixels. The TOT counter is designed to have 8 bits with an overflow control function and the TOF counter is designed to have 14 bits. The preliminary electrical measurement results show that Qpix v.1 can measure TOT and TOF with an accuracy of 10 ns. ADC codes show that the monotonicity is achieved. Compact readout structure in Qpix v.1 provides both parallel and serial readout modes, which guarantees that all the data in one chip can be read out at a high data rate of 240 Mbps. Thus the total time to read out the data in the 400-pixel matrix is 2.6 μ s in parallel readout mode and 54 μ s in serial readout mode. The power consumption has been reduced to 187.5 μ W per pixel. More detailed and accurate measurements of Qpix coupling with gas electron multipliers are in progress.

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms. Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.