Pipelined Array Research Articles

Exploiting data encoding and reordering for low-power streaming in systolic arrays

Systolic Array (SA) architectures are well-suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data movements. Even though most of the dynamic power consumption in SAs is due to multiplications and additions, pipelined data movement within the SA constitutes an additional important contributor. The goal of this work is to reduce the dynamic power consumption associated with the feeding of data to the SA, by employing both dynamic (run-time) and static (offline) techniques. At the hardware level, the proposed architecture synergistically applies bus-invert coding and zero-value clock gating. By exploiting salient attributes of state-of-the-art CNNs, such as the value distribution of the weights, the proposed SA applies appropriate encoding only to the data that exhibits high switching activity. Similarly, when one of the inputs is zero, unnecessary operations are entirely skipped. In addition to this duet of run-time techniques, the proposed methodology also leverages the inherent property of the weight matrix to remain unchanged throughout the inference phase. As such, the weight matrix is appropriately reordered offline to minimize the switching activity between consecutive values, as the matrix is repeatedly loaded into the array. The weight reordering process is formulated as a Traveling Salesman Problem (TSP) and its solution is translated into a switching-activity-aware row permutation of the weight matrix. The symbiotic combination of selectively targeted, application-aware dynamic encoding and offline weight reordering is demonstrated to reduce the switching activity by 38%, on average. This translates to an overall dynamic power reduction of 17.1%–23% when executing state-of-the-art CNN layers on an SA of size 32 × 32. These power savings scale with the array size; for an array of size 64 × 64, the proposed design consumes 29.7%–35.4% less power.

Low power DNA protein sequence alignment using FSM state transition controller

In this paper we proposed an efficient computation technique for DNA patterns on reconfigurable hardware (FPGAs) platform. The paper also presents the results of a comparative study between existing dynamic and heuristic programming methods of the widely-used Smith-Waterman pair-wise sequence alignment algorithm with FSM-based core implementation. Traditional software implication-based sequence alignment methods can not meet the actual data rate requirements. Hardware-based approach will give high scalability and one can process parallel tasks with a large number of new databases. This paper explains finite state machine (FSM)-based core processing element to classify the protein sequence. In addition, we analyse the performance of bit-based sequence alignment algorithms and present the inner stage pipelined field programmable gate array (FPGA) architecture for sequence alignment implementations. Here, synchronised controllers are used to carry out parallel sequence alignment. The complete architecture is designed to carry out parallel processing in hardware, with FSM-based bit wised pattern comparison with scalability as well as with a minimum number of computations. Finally, the proposed design proved to be high performance and its efficiency in terms of resource utilisation is proved on FPGA implementation.

Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata

Cellular arrays have been the topic of interest in computer arithmetic and architecture for the last four decades. In this letter, an overall quantum-dot cellular automata (QCA) design for a generalized pipeline cellular array is presented. QCA is one of the promising emerging nanotechnologies that are being considered as possible alternatives to complementary metal-oxide semiconductor technology due to the physical limitations of CMOS. The QCA designs for arithmetic cell and control cell used in the pipeline array are discussed in detail. The equivalent majority logic networks to these cells are generated using the best existing majority logic synthesis method in order to obtain the optimal majority networks which require fewer QCA cells and clock zones compared to other synthesis methods. The proposed array can perform all the basic arithmetic operations such as squaring, square rooting, multiplication, division, etc., which could be quite valuable in considering future large-scale QCA designs.

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction.

This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures.

A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.

C-slow retimed parallel histogram architectures for consumer imaging devices

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

A Generalized Frame-Level FSBM FLSA Architecture

Block-based motion estimation plays important roles in video applications such as video compression to detect movements as well as remove temporal redundancies between successive frames. Full-search block-matching (FSBM) is the preferred algorithm for accurate motion estimation. Frame-level pipelined systolic array (FLSA) FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation architecture using array processor for any square, N×N, block size is presented in full detail.

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12× and 243×, and energy consumption reduction factors between 13 and 262.

High-performance IP Lookup Engine with Compact Clustered Trie Search

This paper proposes a novel high throughput internet protocol (IP) lookup engine, which is built upon a recently proposed multiple pipeline array architecture that has parallel two-dimensional circular search capabilities on intersecting and variable length pipelines. Our new engine is composed of specially designed processing elements (PEs) including dual input/output static random access memory units and bidirectional links, hence allowing search to proceed in all directions and admitting search requests from all PEs at the boundary of the array. We propose a novel data structure called compact clustered trie (CCT), which is better than traditional binary trie in terms of memory requirement and number of memory accesses. We develop novel approaches including a CCT forwarding table construction method, a mapping strategy and a suitable IP lookup algorithm. Our new lookup engine achieves a much higher average case throughput and a much lower average delay compared with existing IP lookup solutions making, for example, an 8Â Tbps high-speed router front end possible. The engine is also well suited for the IPv6 addressing scheme.

Parallel pipelined array architectures for real-time histogram computation in consumer devices

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle 1.

Research on the Application of Micro-Program Controller in Parallel Neural Networks

In this paper a pipelined array of neurons based on the micro-program controller is proposed as the BP network control circuit implementations, without changing the hardware circuit under the premise of the way by increasing the instruction to meet the BP neural network parallel computing applications to enhance the flexibility of hardware.

Binary multipliers on quantum-dot cellular automata

This article describes the design of ultra-low-power multipliers on quantum dot cellular automata (QCA) nanotechnology, promising very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct structures without the earlier noise problems, verified by the QCA Designer coherence vector simulation. Our results show that the wiring overhead of the arithmetic circuits grows quadratically with the operand word length, and our pipelined array multiplier has linearly better performance-area efficiency than the previously proposed serial-parallel structure. Power analysis at the fundamental Landauer's limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the limits for the clock rates on molecular QCA are much lower, than the switching speeds of the technology.

A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study

A new pipelined systolic array-based (PSA) architecture for matrix inversion is proposed. The pipelined systolic array (PSA) architecture is suitable for FPGA implementations as it efficiently uses available resources of an FPGA. It is scalable for different matrix size and as such allows employing parameterisation that makes it suitable for customisation for application-specific needs. This new architecture has an advantage of O(n) processing element complexity, compared to the O(n2) in other systolic array structures, where the size of the input matrix is given by n × n. The use of the PSA architecture for Kalman filter as an implementation example, which requires different structures for different number of states, is illustrated. The resulting precision error is analysed and shown to be negligible.

A pipelined array architecture for Euclidean distance transformation and its FPGA implementation

The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O( n) hardware algorithm for computing EDT of an n× n image is presented. A pipelined 2D array architecture for harware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Such an array architecture is easily scalable to handle images of different sizes and is suitable for implementation on reconfigurable devices like FPGAs. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512×512 per second which is much higher than the video rate of 30 frames per second.

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design

Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Although Boolean multipliers have natural power-awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A two-dimensional pipeline gating scheme is proposed in this paper to improve the power-awareness in these designs. This technique is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed so that the overhead is hardly noticeable. Simulation results show that an average power saving of 65–66% and latency reduction of 44–47% can be achieved for multipliers under equal input precision probabilities. An application of power-aware multipliers on FIR design is also included.

Real-time area correlation tracker implementation based on absolute difference algorithm

Area correlation tracking is an effective solution for tracking targets that have neither prominent features nor high contrast with the background. We address the implementation of a real-time area correlation tracker (ACT) for an on-board application based on the absolute difference algorithm. The ACT consists of a very high speed and very large scale field programming gate array (FPGA), which contains a special structure of parallel pipelined systolic array to accomplish the correlation computation, and a float-pointed digital signal processor (DSP), which does the parabolic interpolation. The configuration and the timing of the ACT are presented and the ACT is applied successfully in a real-time tracking system. The computation latency for correlation tracking is about 2 ms, which can satisfy the demand of the tracking system used for detecting the solar pore's motion induced by atmospheric turbulence and the mechanical vibrations of the solar telescope. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

Hardware implementation of soft color image morphological operations

A new hardware field programmable gate array (FPGA) structure suitable for the realization of soft color image morphological operations is presented for the first time. Data is processed in a pipelined array that performs fast soft vector erosion and dilation. The proposed hardware structure can process two-dimensional 24-bit resolution color images up to 4096 pixels wide, but it can be easily modified to accommodate larger images. MAX+ PLUS II software of the Altera Corporation is employed for design and simulation. The FPGA used is the EPF10K130VG599-3 Altera device. The typical clock frequency of operation is 40 MHz.

Systolic SVD and QR Decomposition by Householder Reflections

SVD and QR Decomposition have attracted much attention recently for solving linear algebra and digital signal processing problems. The House-holder QR Decomposition requires a smaller number of operations then the Givens QR Decomposition and therefore is strongly recommended for sequential computer implementations (as found in nearly all known libraries like NAG, LINPACK, EISPACK etc.) However for parallel implementation it has not been widely used, because the Givens Rotations possess inherent parallelism and the Householder Reflections do not. This is true if one analyzes the original algorithm. Four independent loops and three bottlenecks between the loops are constraint for pipelining the computations. This leads to an inefficient solution, i.e. 4n time moments for each iteration and since there are n iterations then the total time to execute the algorithm is O(4n 2 ). Compared to 3n m 2 time steps for the Givens QR Decomposition it is uneconomic. In this paper we have used some recent results for the elimination of the computational and data broadcast, and data synchronization to derive a fully localized form of the Householder QR Decomposition algorithm. We have succeeded in reorganizing and transforming the algorithm from three bottlenecks to one and four loops to one. A linear and a double pipeline array of n+1 processors are presented to solve the problem in O ( n 2 /2) time steps. It is also shown that the bottlenecks for the bidiagonalization and SVD computation cannot be eliminated.

Area-time-power tradeoff in cellular arrays VLSI implementations

Designing pipelined cellular arrays for arithmetical purposes, the choice of circuit design style is crucial. Usually, this choice is made by establishing an optimal area-time-power tradeoff. In order to achieve this result, analysis and simulations of the whole designed array have to be repeatedly performed for several design styles. This paper presents a methodology that allows the same result to be obtained avoiding time-consuming simulations of an entire array. The proposed technique is based on an appropriate partitioning of the arrays into small subcircuits. The features of the latter are analytically recomposed to evaluate performances and costs of an array of any size for various design approaches.

A pipelined architecture for image segmentation by adaptive progressive thresholding

A special purpose VLSI architecture for the real-time segmentation of endoscopic images is proposed in this paper. The architecture is based on pipelined implementation of a new algorithm named adaptive progressive thresholding (APT) that segments the darkest region of an endoscopic image representing the gastrointestinal lumen. This segmentation process is an extension of a comprehensive statistical technique based on linear discriminant analysis for partitioning the image. The APT algorithm is mapped onto a linear pipelined array of simple processing elements with each element of a particular segment communicating with its neighbours. The APT architecture is partitioned based on various sequential functions involved in the segmentation process and these functional modules are organised in a pipelined fashion according to their hardware feasibility. Currently, a prototype of the VLSI architecture for an image size of 256×256 is designed and built. The functional simulation results obtained in the APT architecture are encouraging.