Pipelined Processor Architecture Research Articles

Simulation of Pipelined MIPS Floating-Point Units using Node-RED

The pipelined processor architecture is the best way to increase instruction-level parallelism, and thus, understanding its operation is one of the keys in computer architecture learning. To help with the leaning process, we have devised a series of pipeline simulation methodologies. This article presents one of them – a simulation methodology of hazard detection and forwarding in MIPS32 pipelined floating-point units. Our implementation approach is using the Node-RED programming environment, an event-driven dragand-drop system for designing data flows with business logic. In addition, to implement sophisticated operations not supported by Node-RED, we also employ WebAssembly code and the Rust language. We simulate not only the standard 5-stage pipelined MIPS ISA but also pipelined (addition, subtraction, and multiplication) and unpipelined (division) floating-point operations. Our study focuses mainly on hazard detection, which is required to ensure program correctness, as well as forwarding used to improve system performance. Lastly, we design a dashboard interface to visually represent the pipeline stages and CPU status during execution. Using the dashboard interface, MIPS32 machine code can be loaded into our simulator from hexadecimal text files. We verified that our simulator is handling hazard detection and forwarding correctly. A screenshot of the dashboard interface is included that shows all the stages of floating-point pipelines.

A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA

In order to improve the computational efficiency of convolutional neural networks (CNNs) for object detection on reconfigurable platforms such as field-programmable gate arrays (FPGAs), we propose a CNN processor with hierarchical pipelining and multicore reconfigurable computing based on parallel parameter constraints. First, we propose a pipelined multicore processing architecture that can adapt to computations and on-chip memory requirements of different convolutional layers. We present the design of a CNN processor that can configure the computing units while adjusting the interconnection of multicore to improve the utilization of reconfigurable computing resources. Second, we propose an elastic on-chip buffer and a data access approach by dynamically configuring addresses to better utilize on-chip memory. Meanwhile, we present a cross-layer feature map fusion strategy based on computing near memory (CNM) to reduce off-chip memory accesses. Finally, we propose a scheduling algorithm for pipelined tasks to improve the computational efficiency and throughput of the proposed processor. For evaluation, the well-known object detection methods (RetinaNet-ResNet-50, MobileNetV2-SSDLite, and YOLOv3) performed using the proposed CNN processor on the ZCU102 platform and reached the throughput of 1503, 1066, and 809 GOPS and the computational efficiency of 0.79, 0.62, and 0.36 GOPS/DSP, respectively. The designed processor realized a better tradeoff between computing efficiency and detection accuracy compared with the recently proposed object detection CNNs on FPGA.

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP.

Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude consistency, are proposed. In terms of algorithms, we study three beamforming methods, namely delay-and-sum (D&S), direct-method (DM) and Chirp Zeta Transform (CZT). We compare the computational efficiency of DM and CZT in the digital domain. In terms of software, according to the transmission bandwidth of the Gigabit Ethernet and a serial rapid IO (SRIO) interface, the data transmission paths of the acquired data and the beam pattern between the FPGA, the DSP, and a personal computer (PC) are planned. A master-slave multi-core pipelined signal processing architecture is designed based on DSP, which enhances the data throughput of the signal processor by seven times as compared with that of the single-core operation. The experimental results reveal that the sound source level of the transmitting module is around 190.25 dB, the transmitting beam width is 64° × 64°, the background noise of the acquisition module is less than 4 μVrms, the amplitude consistency error of each channel is less than −6.55 dB, and the phase consistency error is less than 0.2°. It is noteworthy that the beam number of the sonar system is 90 × 90, the scanning angle interval is 0.33°, the working distance ranges from 5 m to 40 m, and the maximum distance resolution is 0.384 m. In the positioning experiment performed in this work; the 3-D real-time position of the baffle placed in the detection sector is realized. Please note that the maximum deviation of azimuth is 2°, the maximum deviation of elevation is 2.3°, and the maximum distance deviation is 0.379 m.

P‐57: A Local Histogram Framework for Contrast Enhancement

This paper proposes an implementation framework based on local contrast enhancement (LCE). The framework, implemented on Xilinx Kintex‐7 FPGA platform, is lighted on the 55″ Ultra‐High Definition (UHD) LCD panel and shows the result of image contrast enhancement. In accordance with the hardware design concept, the implementation framework adopts the module partition, hardware parallel processing structure and pipeline processing architecture. The hardware implementation fully achieves the real‐time requirements.

CORDIC-lifting factorization of paraunitary filter banks based on the quaternionic multipliers for lossless image coding

Quaternions have offered a new paradigm to the signal processing community: to operate directly in a multidimensional domain. We have recently introduced the quaternionic approach to the design and implementation of paraunitary filter banks: four- and eight-channel linear-phase paraunitary filter banks, including those with pairwise-mirror-image symmetric frequency responses. The hypercomplex number theory is utilized to derive novel lattice structures in which quaternion multipliers replace Givens (planar) rotations. Unlike the conventional algorithms, the proposed computational schemes maintain losslessness regardless of their coefficient quantization. Moreover, the one regularity conditions can be expressed directly in terms of the quaternion lattice coefficients and thus easily satisfied even in finite-precision arithmetic. In this paper, a novel approach to realizing CORDIC-lifting factorization of paraunitary filter banks is presented, which is based on the embedding of the CORDIC algorithm inside the lifting scheme. Lifting allows for making multiplications invertible. The 2D CORDIC engine using sparse iterations and asynchronous pipeline processor architecture based on the embedded CORDIC engine as stage of processor is reported. Also it is necessary to notice, that the quaternion multiplier lifting scheme based on the 2D CORDIC algorithm is the structural decision for the lossless digital signal processing. This approach applies to very practical filter banks, which are essential for image processing, and addresses interesting theoretical questions.

Functional self-test of high-performance pipe-lined signal processing architectures

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based Logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The on-line generated signal data used for processing in the system serve as test pattern sources. Testing under normal working conditions and with typically processed data, allows exercising of the system on-line and at-speed, facilitating the detection of dynamic faults like delays and cross-talks to achieve high test quality. The proposed new self-test method is free from the negative aspect of over-testing, compared to the traditional Logic BIST approaches, and uses minimal amount of added hardware. Experimental research was based on the case study of specialized bio-signal processor architecture. The experiments showed promising results in reducing the cost of testing and achieving high fault coverage.

A Streaming Distance Transform Algorithm for Neighborhood-Sequence Distances

We describe an algorithm that computes a “translated” 2D Neighborhood-Sequence Distance Transform (DT) using a look up table approach. It requires a single raster scan of the input image and produces one line of output for every line of input. The neighborhood sequence is specified either by providing one period of some integer periodic sequence or by providing the rate of appearance of neighborhoods. The full algorithm optionally derives the regular (centered) DT from the “translated” DT, providing the result image on-the-fly, with a minimal delay, before the input image is fully processed. Its efficiency can benefit all applications that use neighborhood- sequence distances, particularly when pipelined processing architectures are involved, or when the size of objects in the source image is limited.

FPGA-accelerated algorithm for the regular expression matching system

This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

High-Speed Multicast Scheduling in Hybrid Optical Packet Switches with Guaranteed Latency

In this paper, we study multicast scheduling in the OpCut switch, a recently proposed hybrid optical/electronic switching architecture for transmitting high-volume traffic in core networks and parallel computers. First, we present a multicast scheduling algorithm called Guaranteed Latency Multicast Scheduling (GLMS) that considers the schedule of each packet for multiple time slots. We show that GLMS has several desirable features, such as guaranteed latency for all transmitted packets and adaptivity to transmission requirements. To relax the time constraint on computing a schedule, we further propose a parallel and pipeline processing architecture for GLMS that distributes the scheduling task to multiple pipelined processing stages, with N processors in each stage, where N is the switch size. Finally, by implementing it with simple combination logic circuits, we show that each processor can finish the scheduling for one time slot in (O(1)time complexity. We evaluate the performance of GLMS extensively against statistical traffic models and real Internet traffic, and the results show that the proposed GLMS algorithm can achieve very low average packet latency with minimum packet drop ratio.

A pipelined processor architecture for regular expression string matching

The expressive power of regular expressions has been often adopted in network intrusion detection systems, virus scanners, and spam filtering applications. However in the CPU based systems, pattern matching is one of the most computation intensive parts. In this paper, we present the design, implementation and evaluation of a regular expression string matching processing unit (SMPU). This special purpose processor is a parallel and pipelined architecture which can deal with the regular expression semantics. Two hardware stacks are implemented in SMPU to support fast branches when the non-matching occurs. Our implementation processes four characters per clock cycle (maximum performance of state of the art solutions) and occupies only O(n) memory (where n is the length of the regular expression) via synthesizing the verilog description and analyzing area/time constraints, SMPU can achieve 200–400 times speedup over traditional CPU implementations and up to 7.9Gbps in processing throughput. Besides it outperforms the counterparts greatly as the complexity of regular expressions increases.

A framework for traversing dense annotation lattices

Pattern matching, or querying, over annotations is a general purpose paradigm for inspecting, navigating, mining, and transforming annotation repositories—the common representation basis for modern pipelined text processing architectures. The open-ended nature of these architectures and expressiveness of feature structure-based annotation schemes account for the natural tendency of such annotation repositories to become very dense, as multiple levels of analysis get encoded as layered annotations. This particular characteristic presents challenges for the design of a pattern matching framework capable of interpreting ‘flat’ patterns over arbitrarily dense annotation lattices. We present an approach where a finite state device applies (compiled) pattern grammars over what is, in effect, a linearized ‘projection’ of a particular route through the lattice. The route is derived by a mix of static grammar analysis and runtime interpretation of navigational directives within an extended grammar formalism; it selects just the annotations sequence appropriate for the patterns at hand. For expressive and efficient pattern matching in dense annotations stores, our implemented approach achieves a mix of lattice traversal and finite state scanning by exposing a language which, to its user, provides constructs for specifying sequential, structural, and configurational constraints among annotations.

Integrated verification approach during ADL-driven processor design

Nowadays, architecture description languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of application specific instruction-set processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are only applied at register transfer level (RTL) or below. In the context of ADL-based ASIP design, this verification approach is often inconvenient and error-prone, since design and verification are done at different levels of abstraction. In this paper, this problem is addressed by presenting an integrated verification approach during ADL-driven processor design. Our verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design. We show the benefit of our approach by trapping errors in a pipelined SPARC-compliant processor architecture and in an application-specific DSP architecture.

High-Performance Low-Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

NETWORK PROCESSOR FOR HIGH-SPEED NETWORK AND QUICK PROGRAMMING

The paper describes the concept, architecture, and prototype test results of a packet processor that enables us to implement an application-specific high-speed packet processing system without expert-level programming skills. This processor has a pipelined processing architecture and features coarse-grained instructions that are based on the data formats of the telecommunication packet. Using this processor, target applications can be implemented within a short working period without degrading the processing performance. We implemented a prototype system to evaluate its packet propagation delay and packet forwarding performance. The measured results suggest that the architecture is useful for packet processing on high-speed telecommunication networks.

High-speed buffer management for 40 gb/s-based photonic packet switches

We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log/sub 2/N+1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 /spl times/ 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.

A 4-way pipelined processing architecture for three-step search block-matching motion estimation

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Simulation results show that the proposed architecture achieves a high performance for real time motion estimation.

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. A significant bottleneck in the validation of such systems is the lack of a golden reference model. Thus, many existing techniques employ a bottom-up approach to architecture validation, where the functionality of an existing pipelined architecture is, in essence, reverse-engineered from its implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through Architecture Description Language (ADL) constructs, and thus allows a powerful top---down approach to architecture validation. The most important requirement in top---down validation process is to ensure that the specification (reference model) is golden. Earlier, we have developed validation techniques to ensure that the static behavior of the pipeline is well-formed by analyzing the structural aspects of the specification using a graph based model. In this paper, we verify the dynamic behavior by analyzing the instruction flow in the pipeline using a Finite State Machine (FSM) based model to validate several important architectural properties such as determinism and in-order execution in the presence of hazards and multiple exceptions. We applied this methodology to the specification of a representative pipelined processor to demonstrate the usefulness of our approach.

Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters

The optimum architecture design and mapping of QRD-RLS adaptive filters can be achieved through filter architecture selections, look-ahead transformations, and hierarchical pipelining/folding transformations. In this paper, a relaxed annihilation-reordering look-ahead (RARL) architecture is proposed, and shown to be more power and area efficient than pipelined processing architecture which was considered the most area efficient. The filters with this architecture are based on relaxed weight-update through filtering approximation, where a filter tap weight is updated upon arrival of every block of input data, and are speeded up with annihilation-reordering look-ahead transformation. As a result of the computational complexity reduction, this architecture does not change the iteration bound and filter clock frequency, and leads to speed up with linear increase in power consumption, while the pipelined processing architectures result in speedup with quadratic increase in power consumption. Upon hardware mapping, this architecture is also more advantageous to achieve low area designs. Two design examples are presented to illustrate mapping optimization using above transformations. These results are important for mapping designs onto ASICs, FPGAs or parallel computing machines. The results show significant improvements in throughput, power consumption and hardware requirement. It is also interesting to show through mathematics and simulations that the RARL QRD-RLS filters have no performance degradation in terms of convergence rate.

High-Speed Computation of Distinct Element Method by Pipelined Processors.

Distinct Element Method, or DEM, is considered practical and applied to many kinds of numerical analysis; however, it requires a lot of calculation time. A new method, which accelerates computation speed by 3.1 to 31 times, is presented in this paper. A pipelined processor architecture is employed to enhance the process of making a list of contact elements, which needs N2 calculation cost, where N is the number of elements. In addition, the calculation precision of the processors is reconfigurable, that is, either 32 bit floating or 32 bit fixed point precision can be implemented on a single hardware when to operate. That is achieved by making use of FPGA, or Field Programmable Gate Array, which is a dynamically rewritable logic device. Through experiments, it is confirmed that our method works as was expected, and is effective.

Optimal parallel and pipelined processing through a new class of matrices with application to generalized spectral analysis

A new class of general-base matrices, named sampling matrices, which are meant to bridge the gap between algorithmic description and computer architecture is proposed. Poles, zeros, pointers, and spans are among the terms introduced to characterize properties of this class of matrices. A formalism for the decomposition of a general matrix in terms of general-base sampling matrices is proposed. Span matrices are introduced to measure the dependence of a matrix span on algorithm parameters and, among others, the interaction between this class of matrices and the general-base perfect shuffle permutation matrix previously introduced. A classification of general-base parallel recirculant and parallel pipelined processors based on memory topology, access uniformity and shuffle complexity is proposed. The matrix formalism is then used to guide the search for algorithm factorizations leading to optimal parallel and pipelined processor architecture. >