A 4-way pipelined processing architecture for three-step search block-matching motion estimation

Abstract

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Simulation results show that the proposed architecture achieves a high performance for real time motion estimation.