Pin Count Research Articles

Highly robust soft-rigid connections via mechanical interlocking for assembling ultra-stretchable displays

Stretchable electronic circuits can seamlessly conform to irregular and dynamic surfaces with high integration. However, current stretchable configurations typically have limited stretchability due to the lack of robust connections between soft interconnects and rigid electronics. Here, we printed highly stretchable metal–polymer conductors on thermoplastic elastomers as interconnects. We developed electronic vests with porous surfaces for rigid electronics and introduced polyester hot-melt adhesives to strengthen connections between soft interconnects and rigid electronics. After thermal bonding, the adhesive penetrates the porous surface of electronic vests, creating a mechanical interlock and providing an adhesion force of 8.34 N/cm for the connection (3× higher than conductive adhesives). Thus, rigid electronics of different sizes and different pin counts can form strong connections to soft interconnects, achieving a maximum strain tolerance of ~700% (10× higher than conductive adhesives). We achieved highly integrated ultra-stretchable displays that can withstand stretching up to 220% without dead pixels.

WLCSP Fully Protected Fan-In Reliability

A strong supply chain requires higher performance and lower cost processes. DCA conventionally referred to as WLCSP has been used for low density devices, however for higher density devices reliability concerns have emerged. Six-side protected, aka “6S or fully protected”, CSP is a rapidly growing market. Fully protected CSP was first implemented with processes such as M-series utilizing FO. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations. These steps can be eliminated in a P-WLCSP process to provide the cost-effective high reliability 6S format needed for high-performance higher pin count and/or thin silicon chips. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking and thin board applications. The P-WLCSP process incorporates the best of DCA (simplicity) and FO (protection) while incorporating advanced manufacturing processes to lower cost and improve performance. This paper builds on the SoP-TM process release announced at the 2023 Device Packaging Conference earlier this year with the addition of reliability characterization beyond first silicon data for electrical test chips. Reliability data such as accelerated stress tests, die strength, operating lifetime and thermal testing are key areas of investigation for the new P-WLCSP technology that will be presented. The presentation will also include and update for ultra-thin device reliability test methods under consideration for new NIST standards.

Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications

Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications

Incorporating Hierarchical Construction for Advanced IC Packaging

Advancements in IC packaging manufacturing have given rise to the growing trend disaggregating large SoC into smaller die/chipets. This significantly raises the barrier for IC package designers with increasing design complexity and exploding pin counts. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production. In this paper, we present a new approach IC package floor-planning using hierarchical device modeling system assembly. The key benefit of adopting hierarchy inside of a design is clear – a seemingly large and complex design can be disaggregated into smaller and easier to manage building blocks based on collection attributes such as function and position. In IC packaging there are two key classes of design structures which lend easily to disaggregation. These are die-to-die signal interfaces and power distribution networks. Die to die signal interfaces are implemented as uniform signal bump collections placed at least twice in the system but usually used several times to link several dies. Similarly, power distribution networks typically replicated in several regions of the system design and the bump assignment often assigned to meet a specific physical implementation such as checker-board bump pattern for a two-layer power ground mesh. These design structures can in turn be placed or arrayed in various combinations to create larger composite building blocks in the full design assembly. Yet unlike in IC design, the key challenge with adopting hierarchical device modeling in IC packaging is that the top-level floorplan demands a unique signal connectivity definition regardless of the placement hierarchy. While there are brute force methods of doing this such as performing manual connectivity edits to add prefixes of suffices to the top-level signal, these are time consuming and error prone – particularly when design updates are required. To properly address the top-level connectivity, this paper introduces a novel method to assign connectivity based on topological pin regions defined over bump collections which can then be used to automatically define the top-level connectivity bump based on system attributes such as the parent instance and region names. Using topological pin regions in hierarchical construction allows design updates at the building block level to instantly propagate to the full design. Package designers need to employ all tools available to address the significant device complexity and an explosion in pin count in today’s IC packaging designs. Through hierarchical device modeling construction with topological region-based connectivity, we highlight that large and seemingly complex designs are easily broken down into easily manageable building blocks.

Efficient Temporal Arithmetic Logic Design for Superconducting RSFQ Logic

In this paper, we propose a temporal decimal multiplier design that reduces the area and pin count compared to an equivalent binary multiplier. In this design, we have efficiently embedded time-to-decimal conversion inside the logic, which mitigates the need for external conversion circuits. Also, our design mitigates a drawback of temporal logic that typically requires ‘n' time delays to represent ’n' numerical values, which results in longer latency for large values of ‘n‘. By representing numbers as parallel temporal values where each value represents a different digit (0-9) of the number, we reduce the maximum delay needed to represent the product to only 9 delay (clock) cycles for any multiplication outcome. We show performance and area benefits for different temporal multiplier designs with fully-laid out, tapeout-ready design implemented in MITLL's SFQ5ee process. Compared to a 4-bit binary multiplier, our temporal decimal multiplier reduces the pin count by approximately 3× and the area by 40%. Finally, we evaluate our proposed temporal multiplier against conventional binary multipliers when configured for DSP and machine learning algorithms.

Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis

Scan chain diagnosis is an important step in solving yield problems in early manufacturing processes. The higher the diagnostic resolution, the better the yield in the initial process. In the conventional scan chain architecture, if failed scan chain data are observed during scan mode, all the shifted data through a stuck-at faulty cell are contaminated. As a result, only a single fault can be diagnosed, and there are difficulties in diagnosing multiple stuck-at fault locations. The number of multiple faults has increased significantly, increasing the cost of physical fault analysis. In addition, it is difficult to diagnose faults with a high resolution because there are many candidate faults early in the process. In this paper, a new hardware architecture with data duplication is proposed to diagnose fault locations by deliberate voltage collision even if multiple faults occur. The resources required for the diagnosis include a minimum of one good scan chain, a diagnosis circuit, and a diagnostic line. Experimental results show that the proposed method has lower hardware and routing overhead and fewer additional pin counts than the existing method. The diagnostic speed is also faster, and the larger the number of scan chains (the larger the circuit), the higher the diagnostic performance, which has advantages over conventional methods.

Optimized design of an extreme low power datalogger for photovoltaic panels

<span lang="EN-US">The paper focuses on the design and implementation of a low cost and compact data logger prototype using an extreme low power (XLP) and low pin count programmable interface controllers (PIC) microcontroller using its own flash memory for the periodic data acquisition storage, while many other works focus in the Arduino Eco-system. It is planned to pick four important analog measures from the photovoltaic system, and store them directly as 10-bit numerical counts, this yields to faster data acquisition and storage (no time consuming for mathematical computation to convert each numerical count of raw data to meaningful real-world data). Avoiding the use of any kind of display and keypad, and keeping the ratio run time over sleep time as low as possible, has a maximum impact on lowering the power consumption. This prototype can be serially linked to a personal computer (PC) to view the acquisition of measurements in real time, and to retrieve all collected data through a terminal application. The experimental results are stored in comma-separated values (CSV) files to ease post data analysis with any spread sheet software, for statistical calculations and graphs drawing, in order for instance, to find the faults of the photovoltaic system and optimize its management and its performance.</span>

Digital Twins and Smart Manufacturing for Wire Bonding

Low cost, excellent flexibility, and high yield rate have long been the drivers of wire bonding technology. In the past decade, advancements in wire bonding technology have significantly improved wire bond reliability and strengthened the adoption of the technology while maintaining its competitive advantage. Digital twins of wire bonding can now simulate and optimize 3D wire loop shapes to facilitate design-for-manufacturing (DFM), increase design flexibility, reduce product development time, and improve overall package yields. In particular, the benefits of digital twins have been realized in system-in-package (SiPs), large stack-die memory applications, and complex high pin count packages with multiple looping tiers. With increasing package complexity and modular package configurations, the need for smarter functionalities is imperative. More recently, technological developments in wire bonding have been targeted toward furthering design, quality, and time-to-market (TTM) from an Industry 4.0 smart manufacturing perspective. In this paper, we will introduce new digital twin simulation techniques to detect potential interference between wire bond capillaries and wire loops, various dies, passive components, and other structures within the package. These advanced capabilities are demonstrated on a real application and shown to help in the detection of design issues early in the product cycle and aid in the selection of capillary, wire, as well as optimization of the package layout. All these factors significantly improve the overall TTM of semiconductor packages. Technologies that provide improvements via autonomous monitoring and optimization are also strongly desired. We will also explore new on-bonder process monitoring capabilities to detect wire sway such that wire shorts and resultant yield losses can be minimized. Additionally, vision-guided enhancements to on-bonder loop height monitoring capabilities will also be discussed. These new advancements significantly improve production quality and yield, paving the way for smarter factories

Liquid Metal Based Low Resistance Interconnect Technology

There is an increasing desire for interconnect technologies that provide low contact resistance, shorter electrical path and enable pin count scaling without the need for complex loading mechanisms. Ball grid array (BGA) technologies provide some of these benefits but add the complexity of surface mount challenges, especially on large form factor packages. Furthermore, customers value the flexibility of late and separable attach capability that sockets provide. Sockets, however come with a higher contact resistance and the required compression force drives significant cost and complexity to the loading mechanism. A liquid metal-based socket interconnect technology is introduced that offers BGA like performance with the benefits of a traditional socket. The liquid metal being studied is a gallium based eutectic alloy with a low melting point. The measured contact resistance is the lowest amongst available socket technologies and is equivalent to a permanently soldered down connection. The paper describes a process to manufacture a liquid metal interconnect and electrical characteristics of such an interconnect. This technology is in its infancy with insufficient data on field reliability risks or potential failure mechanisms when used as an interconnect. However, traditional evaluation techniques are less relevant for this novel interconnect and new methodologies are introduced to evaluate this technology.

A Hybrid Test Scheme for Automotive IC in Multisite Testing

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.

Self-compassion manipulation regulates affect and aggressive inclinations in the context of social rejection

Three studies (combined N = 1035) tested whether inducing a self-compassionate state of mind would help people regulate affect and aggressive inclinations toward rejecters. State self-compassion, negative affect, and pin counts in the voodoo doll task were assessed across all the studies, positive affect was assessed in Studies 2 and 3, and calm affect and revenge intention were assessed in Study 3. Compared with those in the control condition, participants in the self-compassion condition reported higher levels of state self-compassion (Studies 1 to 3), positive affect (Studies 2 and 3), and calm affect (Study 3), and lower levels of negative affect (Studies 1 to 3) and revenge intention (Study 3). A mini meta-analysis showed that participants in the self-compassion condition selected fewer pins to stab into a voodoo doll. Mediation analyses further suggested that negative affect and calm affect played mediator roles in the association between self-compassion manipulation and aggressive inclinations.

Study of robust package strength characterization of memory packages for handheld application

In mobile market, the demand of memory packaging increase year over year. While the form factor of memory packages moves toward smaller and thinner geometry with higher pin counts, the package overall mechanical robustness becomes one of a key criteria for mobile companies regarding to consumer usage condition. Package strength is an indicator for package robustness. Package with low strength may likely lead to die cracking or epoxy mold compound (EMC) cracking during assembly, testing, reliability testing or consumer field usage. In this study, comprehensive factors will be covered to discuss the impact on package strength performance. In addition, the failure analysis would be studied aiming to observe initial crack point. Last, the study will discuss about the current testing methodology and will later propose new testing methodologies which are more suitable to field application condition.

RLC Circuit Forecast in Analog IC Packaging and Testing by Machine Learning Techniques.

For electronic products, printed circuit boards are employed to fix integrated circuits (ICs) and connect all ICs and electronic components. This allows for the smooth transmission of electronic signals among electronic components. Machine learning (ML) techniques are popular and employed in various fields. To capture the nonlinear data patterns and input–output electrical relationships of analog circuits, this study aims to employ ML techniques to improve operations from modeling to testing in the analog IC packaging and testing industry. The simulation calculation of the resistance, inductance, and capacitance of the pin count corresponding to the target electrical specification is a complex process. Tasks include converting a two-dimensional circuit into a three-dimensional one in simulation and modeling-buried structure operations. In this study, circuit datasets are employed for training the ML model to predict resistance (R), inductance (L), and capacitance (C). The least squares support vector regression (LSSVR) with Genetic Algorithms (GA) (LSSVR-GA) serves as an ML model for forecasting RLC values. Genetic algorithms are used to select parameters of LSSVR models. To demonstrate the performance of LSSVR models in forecasting RLC values, three other ML models with genetic algorithms, including backpropagation neural networks (BPNN-GA), random forest (RF-GA), and eXtreme gradient boosting (XGBoost-GA), were employed to cope with the same data. Numerical results illustrated that the LSSVR-GA outperformed the three other forecasting models by around 14.84% averagely in terms of mean absolute percentage error (MAPE), weighted absolute percent error measure (WAPE), and normalized mean absolute error (NMAE). This study collected data from an IC packaging and testing firm in Taiwan. The innovation and advantage of the proposed method is using a machine approach to forecast RLC values instead of through simulation ways, which generates accurate results. Numerical results revealed that the developed ML model is effective and efficient in RLC circuit forecasting for the analog IC packaging and testing industry.

Two-Layer Rt-QFN: A New Coreless Substrate Based on Lead Frame Technology

Lead frames have been widely used in the semiconductor package assembly industry; a lot of demand is still maintained in fields requiring high reliability, such as automobiles, although many fields are being replaced by laminated substrates according to the recent electronic package product trend that requires high I/O pin count. The purpose of this paper is to introduce two-layer Rt-QFN, one of the lead frame-based coreless substrates. (Rt-QFN is a trademark of Haesung DS, which means premold type lead frame substrate.) two-layer Rt-QFN can secure more advanced design freedom compared with the lead frame and thus has I/O pin count coverage intermediate between the lead frame and laminated substrate. In addition, Rt-QFN can exhibit excellent heat dissipation performance by replacing via holes of the laminated substrate with Cu bumps formed by etching. CAE analysis showed that the thermal resistance of the two-layer Rt-QFN substrate was about 23% lower than that of the laminate substrate. The excellent heat dissipation property of two-layer Rt-QFN allows it to replace the existing expensive ceramic substrate and can achieve cost savings. In addition, the sputtering technique, including the LIS (Linear Ion Source) module, was introduced as a method to sufficiently secure the interfacial adhesion between the resin/Cu interface, which is a key factor in producing a two-layer substrate. As a method to enhance the interfacial adhesion between the resin/Cu interface, the collimated mode of LIS was used in the Ar atmosphere inside the vacuum chamber to activate the resin surface. After plasma pretreatment on the surface of the resin, a Cu seed layer was continuously formed by sputtering. As a result, it was possible to secure the high reliability of the two-layer Rt-QFN substrate, and it was confirmed through the evaluation of interfacial adhesion of more than 1.2 kgƒ/cm during the peel-off tape test at the resin/Cu interface and further moisture absorption evaluation.

Improving Hardware Security on Talos II Architecture Through Boot Image Encryption

The OpenPOWER Foundation is an organization that promotes open-source high-performance hardware like the POWER9. OpenBMC is an OpenPower project that strives to produce an open-source firmware stack for Baseboard Management Controllers (BMCs). If hardware falls into the hands of competitors or bad actors, reverse engineering methods can be used to leak or manipulate sensitive information from the boot sequence. This represents a security concern because the root of trust can be invalidated. For example, since the Initial Program Load (IPL) data is frequently not encrypted and is sent over the Low Pin Count (LPC) bus, it is possible to intercept and conduct man-in-the-middle attacks to modify the boot process. The boot image flash chip could also be removed from the Talos II motherboard and examined by competing server architecture manufacturers to reveal detailed boot information. Firmware that developers deem to contain sensitive code or perform innovative operations needs to be protected before being flashed onto the boot image chip. This paper demonstrates a method to encrypt sections of the boot image by encrypting a section of the image before flashing it onto the Talos II. The encrypted image will be decrypted during the boot sequence in the Level 3 cache of the POWER9, proving that it is possible to prevent adversaries from interfering with the IPL flow or obtaining details on firmware from the flash chip. This paper presents a novel method to improve the security of the boot image on Talos II architecture by encrypting the boot firmware image and decrypting it during the boot process. The proof of concept was executed on a Raptor Engineering Talos II system running a POWER9 processor with OpenBMC firmware on the ASPEED AST2500 BMC. This research claims that this unique method increases boot time security through firmware without altering hardware.

High Density Package Design Platform and Assembly Design Kit

Abstract With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design. In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.

An Integrated Co-Design of Flow-Based Biochips Considering Flow-Control Design Issues and Objectives

With increasing effectiveness of flow-based microfluidic biochips in the field of biochemical experiments and point-of-care diagnosis, design automation demands enormous attention to integrate the flow-layer design and control-layer design instead of considering them in isolation. Some severe design issues like valve reliability, control-channel delay, pressure skew, etc. are obvious and they must be tactfully dealt along with minimization of several cost-driving issues like schedule length, pin count, and control-channel length while ensuring planarity of the flow-layer components as well as control-layer channel routes. Hence, this paper aims to propose a unified flow-control co-design methodology considering various flow-control cost-driving issues while reducing the design cycles to obtain a low-cost and efficient platform. The performance is evaluated over several benchmark bioassays that show the efficacy of the proposed co-design method which reduces the number of required valves by 30%, control-channel length by 48.5%, and number of flow-channel crossings by 72.2% than the existing works, on an average.

A 3-D Reconfigurable Memory I/O Interface Using a Quad-Band Interconnect

This article presents a 3-D reconfigurable memory I/O transceiver using a quad-band interconnect (QBI). The 3-D QBI provides I/O data reconfigurability, decreases latency, and reduces pin count for future compact mobile memory interfaces. The 3-D integrated circuit (3-D IC) technique is utilized to reduce signal latency and improve signal integrity. A novel quad-band transformer is proposed to achieve reconfigurable four-band data communication and reduce the I/O pin count by four times. A two-tier QBI die-stack is implemented to verify the QBI design. Face-to-face configuration with $\mu $ bump interconnects is used to save cost. The QBI chips are designed and fabricated in a 180-nm CMOS process. The chip areas of the top and bottom dies are 1.77 and 1.4 mm2, respectively. The measured data rates, with bit error rate (BER) $ , are up to 2 Gb/s in the baseband (BB) and 2.3, 2.5, and 3 Gb/s in RF-bands. The QBI energy efficiencies, with a 1.8-V supply voltage, are 5.9 pJ/b in the BB and 6.2, 7.4, and 8 pJ/b in the RF-bands.

Prepaid Energy Metre with Theft Detection System

The living arrangement of power charging in India is mistake Inclined and further more hour and work devouring. It is included different theme belike power robbery. As a piece of measure to make power available to each indian. We have presented the prepaid energy metre with burglary location framework. It is plan and build up a wise energy metreing framework that can productively be monitoring the measure of power devoured by client. The client gets message on their cell phones about the units they bought by means of G.S.M. innovation. Prepaid energy metre is another idea in estimation of power utilization on intermittent premise. In this structure a shrewd energy metre is proposed in every shopper ace and worker is kept up at the expert co-op party. Customers can undoubtedly energize their energy metre by supplicant a PIN count included up in a scrape bookmark to the worker utilizing SMS. In the current work, the creator has planned and built up another computerized energy metre which is associated with the viable microcontroller, a showcase gadget and viable programming to catch, communicate and keep up the record of the power utilization information of a specific client. The PIC miniature regulator recognized how much units the client have bought and the hand-off was exchanged appropriately. At the point when the units bought got equivalent to the units devoured, the transfer played out its capacity by switch off the power framework. The admonition message was shipped off client versatile through G.S.M. innovation before the disengagement of power.

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.