Physically Unclonable Functions Implementations Research Articles

Забезпечення управління цифровими правами для створення штучного інтелекту як сервісу на основі FPGA реалізації

The subject of study in this article is modern FPGA technologies for creation of projects and providing them as a services, as well as solutions for ensuring digital rights management of individual instances of the system. The goal is to analyze and improve technologies for ensuring the work of licensing mechanisms and prevention of unauthorized execution of IP-cores involved in the implementation of artificial intelligence (AI) systems in FPGA. Task: to analyze the process of prototyping artificial intelligence systems and providing them as a services using FPGA; to perform an analysis of the possibility of the implementation of a rental mechanism for artificial intelligence as a service based on FPGA with licensing of individual instances of the system; to analyze the possibilities of code protection for the description of the implementation of service rental mechanisms directly in the FPGA; to perform research of possible candidate elements that allow uniqueness identification of individual instances of the system or FPGA chip; and to provide practical example of the application of mechanisms for ensuring digital rights management for creation of artificial intelligence as a service project in FPGA. According to the tasks, the following results were obtained. The analysis of technological capabilities, tools and development environments, description and programming languages for the creation of artificial intelligence systems in the form of a service with hardware implementation is performed. The components of each level of FPGA-based AI service implementation are analyzed. An analysis of possible directions for ensuring digital rights management for AI services projects in FPGA is performed. The possibility of protecting the source code of the description of hardware solutions for the possibility of distribution using the IEEE-1735 encryption standard is analyzed. The integration of the encryption standard with the development environments is discussed. A search of options and possible solutions to ensure identification of the specific instance of the project based on FPGA chip is performed. A practical study of the use of the existing solution from Accelize company for ensuring digital rights management for IP-cores of projects for FPGA is performed. Conclusions. The main contribution and scientific novelty of the obtained results is in the provided results of the research of possible candidate elements that allow the detection of differences and identification of the FPGA uniqueness for the identification of the instance of the system. The proposed method of processing of data from the implementation of physical unclonable functions (PUF) in FPGA to ensure digital rights management is a principal new approach. The given relations between the levels of implementation of AI as a service based on FPGA show the hierarchy of components when building of such system.

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.

Voxelated opto-physically unclonable functions via irreplicable wrinkles

The increased prevalence of the Internet of Things (IoT) and the integration of digital technology into our daily lives have given rise to heightened security risks and the need for more robust security measures. In response to these challenges, physical unclonable functions (PUFs) have emerged as promising solution, offering a highly secure method to generate unpredictable and unique random digital values by leveraging inherent physical characteristics. However, traditional PUFs implementations often require complex hardware and circuitry, which can add to the cost and complexity of the system. We present a novel approach using a random wrinkles PUF (rw-PUF) based on an optically anisotropic, facile, simple, and cost-effective material. These wrinkles contain randomly oriented liquid crystal molecules, resulting in a two-dimensional retardation map corresponding to a complex birefringence pattern. Additionally, our proposed technique allows for customization based on specific requirements using a spatial light modulator, enabling fast fabrication. The random wrinkles PUF has the capability to store multiple data sets within a single PUF without the need for physical alterations. Furthermore, we introduce a concept called ‘polyhedron authentication,’ which utilizes three-dimensional information storage in a voxelated random wrinkles PUF. This approach demonstrates the feasibility of implementing high-level security technology by leveraging the unique properties of the rw-PUF.

Exploitation of OTFTs variability for PUFs implementation and impact of aging

Commercial Organic Thin Film Transistors (OTFT) have been characterized to evaluate their variability and reliability. The feasibility of implementing Physical Unclonable Functions (PUFs) based on these devices has been evaluated, taking advantage of the high variation in the electrical characteristics among different OTFTs. The eventual impact of device aging on PUFs reliability has been preliminary explored.

Hardware-Intrinsic Physical Unclonable Functions by Harnessing Nonlinear Conductance Variation in Oxide Semiconductor-Based Diode

With the advancement of the Internet of Things (IoT), numerous electronic devices are connected to each other and exchange a vast amount of data via the Internet. As the number of connected devices increases, security concerns have become more significant. As one of the potential solutions for security issues, hardware intrinsic physical unclonable functions (PUFs) are emerging semiconductor devices that exploit inherent randomness generated during the manufacturing process. The unclonable security key generated from PUF can address the inherent limitations of conventional electronic systems which depend solely on software. Although numerous PUFs based on the emerging memory devices requiring switching operations have been proposed, achieving hardware intrinsic PUF with low power consumption remains a key challenge. Here, we demonstrate that the process-induced nonlinear conductance variations of oxide semiconductor-based Schottky diodes provide a suitable source of entropy for the implementation of PUF without switching operation. Using a mild oxygen plasma treatment, the surface electron accumulation layer that forms naturally in oxide semiconductor film can be partially eliminated, resulting in a large variation of nonlinearity as an exotic entropy source. The mild plasma-treated Schottky diodes showed near ideal 50% average uniformity and uniqueness, as well as an ideal entropy value without the need for additional hardware area and power costs. These findings will pave the way for the development of hardware intrinsic PUFs to realize energy-efficient cryptographic hardware.

CurIAs: Current-Based IC Authentication by Exploiting Supply Current Variations

Physical unclonable functions (PUFs) have emerged as one of the most notable hardware primitives to mitigate the ever-growing global issue of counterfeiting and cloning of integrated circuits (ICs) in recent times. PUFs exploit the intrinsic manufacturing process-induced parametric variations for generating unique chip identifiers. However, most of the existing PUF implementations require complex structures or the inclusion of additional components, which incur performance and area overheads. In this work, we introduce <i>CurIAs</i> , a supply current-based novel PUF implementation to authenticate ICs and to protect them from counterfeiting attacks. It exploits the dynamic current stemming from temporal switching activities in existing on-chip structures as an entropy source to generate high-quality IC-specific digital signatures. First, we investigate the source of the entropy of this PUF, <i>i.e.</i> , the dynamic current variations in different circuit structures, with transistor-level Monte-Carlo simulations in HSPICE. Next, to evaluate its effectiveness in Silicon, we apply this approach to map LFSR (Linear Feedback Shift Register) designs into 20 FPGA chips (fabricated in TSMC 55nm process node), perform practical measurements, and generate digital signatures. These signatures show high uniqueness, robustness, uniformity, and randomness features, and the overall implementation requires modest hardware overhead ( <inline-formula><tex-math notation="LaTeX">$&lt;$</tex-math></inline-formula> 1%). We assess and substantiate the robustness of this approach at eight different operating points by varying supply voltage and temperature. Furthermore, we upscale the design to more extended LFSR sizes, and it exhibits a constant trend of performance improvement over the operating points. Through a judicious selection of challenge vectors, <i>CurIAs</i> demonstrates a high resilience against model learning attacks, with an average prediction accuracy of 50%. These intrinsic variations in supply current across ICs for varying workloads entail unique chip-specific signatures, which are extremely difficult to clone, and can be deployed effectively against IC counterfeiting issues.

FPGA implementation of PUF based key generator for secure communication in IoT

Various security measures for IoT devices have been introduced in recent years. One of the improvements is through the addition of cryptographic hardware along with the central core processor. As IoT devices are resource-constrained, area and power-efficient solutions are needed. Every cryptographic algorithm has a key generator that provides proper keys to encrypt and decrypt the data. This paper focuses on improving the key generators using Physical Unclonable Functions (PUFs). Execution of NIST-STS randomness test and evaluation of crucial performance parameters is done for the generated bit-stream by proposed PUF design. The proposed design is also compared with three designs from the literature based on area and power consumption which are essential parameters for resource-constrained IoT devices. For proposed design number of LUTs, FFs and power consumption are decreased up to 80%, 76% and 67%, respectively, when implemented on Xilinx Artix-7 FPGAs.

Nano-intrinsic security primitives with redox-based resistive memory

Physical unclonable function (PUF) exploits advantages of otherwise undesirable non-idealities to create physical systems that are difficult to copy even with the same manufacturing process. Nano-intrinsic PUFs use the variability of nanotechnology per hardware instance as a source of cryptographic randomness. Among various emerging memories, redox-based resistive memory (ReRAM) is a promising candidate for providing next-generation low-cost, low-power, ultra-small PUF-based security solutions. This review shows various ReRAM-based PUF implementations and their key features. We compare their performance and discuss which properties of ReRAM to focus on for effective PUF implementation.

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation.

Secure lightweight obfuscated delay-based physical unclonable function design on FPGA

The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware fingerprinting technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay-based PUF on the FPGA board. The delay analysis result proves that our method to implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%.

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

Physically unclonable functions (PUFs) are recently utilized as a promising security solution for authentication and identification of internet of things (IoT) devices. In this article, we present an efficient implementation of XOR Arbiter PUF (XOR APUF) on field-programmable gate arrays (FPGAs). In our work, we incorporated concept of discrete programmable delays logic (PDL) configurations, the obfuscated challenges and temporal majority voting (TMV) before the XOR operation concurrently to enhance uniqueness and security. The derived design has been verified on 25 Xilinx Artix-7 FPGAs and the results are promising with uniqueness of 48.69%, uniformity 50.73% and reliability 99.41%, which significantly improves over previous work into XOR APUF designs. In addition, we also investigate modeling attack resistance of the proposed design against various modelling attacks and the security analysis show that the proposed PUF has lower prediction rate (<65%) when compared to the previous XOR APUF designs.

PUF Implementation Using Competing OTPM Devices in Novel 5T-2OTPM Differential Configuration

Physical unclonable function (PUF) is an important circuit component for realizing cyber-physical security of data and electronic systems. In this work, we present a low-cost PUF implementation using metal-insulator-metal (MIM)-type PECVD SiO₂-based one-time programmable memory (OTPM) devices. We present a custom Verilog-A compact model of OTPM devices for complete PUF hardware implementation in the 180-nm CMOS technology. The implementation of PUF scheme based on a novel differential bit cell using OTPM devices shows strong performance in terms of uniqueness, reliability, and uniformity without additional overheads in terms of bit error correction and postprocessing.

A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> with the proposed ESS scheme applied.

Quantum Physical Unclonable Functions: Possibilities and Impossibilities

A Physical Unclonable Function (PUF) is a device with unique behaviour that is hard to clone hence providing a secure fingerprint. A variety of PUF structures and PUF-based applications have been explored theoretically as well as being implemented in practical settings. Recently, the inherent unclonability of quantum states has been exploited to derive the quantum analogue of PUF as well as new proposals for the implementation of PUF. We present the first comprehensive study of quantum Physical Unclonable Functions (qPUFs) with quantum cryptographic tools. We formally define qPUFs, encapsulating all requirements of classical PUFs as well as introducing a new testability feature inherent to the quantum setting only. We use a quantum game-based framework to define different levels of security for qPUFs: quantum exponential unforgeability, quantum existential unforgeability and quantum selective unforgeability. We introduce a new quantum attack technique based on the universal quantum emulator algorithm of Marvin and Lloyd to prove no qPUF can provide quantum existential unforgeability. On the other hand, we prove that a large family of qPUFs (called unitary PUFs) can provide quantum selective unforgeability which is the desired level of security for most PUF-based applications.

A Homogeneous, Reconfigurable, and Efficient Implementation of PUF in 3-D Selector-Free RRAM

Hardware encryption primitives such as physical unclonable functions (PUFs) are used in power and cost limited Internet of Things (IoT) and computing on edge devices. Resistive random access memory (RRAM) PUF is proposed as an alternative to CMOS one. But due to the existence of transistors as selectors, it still shares the drawbacks of CMOS PUF. In this work, a homogeneous and efficient PUF was constructed out of 3-D selector-free RRAM. It is immune to ray attack and fault injection and features low power, thanks to the absence of transistors and high-resistance states of the RRAM cells. The inter- and intra-Hamming distances (HDs) are measured to be 50.02% and 0%, respectively, which well validates its uniqueness and reliability. Experimental results show that the proposed PUF can be operated with a low energy consumption of 144 fJ/bit, and a compact bit-cell area of 16 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit. The digital values in the cells can maintain for over 100 h at 85 °C, which is equivalent to 24 years under 40 °C. Besides, given that the selector-free structure renders the PUF instance homogeneous, the PUF instance has enhanced security performance against radiation.

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Leakage free helper data storage in microcontroller based PUF implementation

Physical Unclonable Function (PUF) generates a unique identifier of a device, based on variations during a manufacturing process. Such identifier is difficult to predict or clone. It is used usually as a cipher key. Its weakness is, in general, a high sensitivity to changes in environmental conditions. In order to ensure stability, post-processing methods with error correction codes are usually applied. Unfortunately, these methods reveal, in many cases, sensitive data. We present a novel way to apply error correction code for the PUF. It is called Code Word Masking construction. This construction allows to generate PUF response in more secure way. Helper data are formed just by properly selecting PUF response bits. Therefore, helper data do not leak sensitive information. The selection is performed according to code words of the error correction code used. The method can be used for any type of weak PUF and many types of error correction codes. The error correction capability of the construction depends only on the capability of the error correction code. We describe this construction, and present an example of the PUF implementation based on the non-initialized values of the static random access memory using a 32-bit microcontroller. The implementation is more secure and has lower entropy loss compared to existing solutions. The reliability of the solution was proved through measurements under various environmental conditions. The implementation is improved by identifying and excluding the unreliable (’dark’) bits.

Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor

The robustness of Static random access memory (SRAM) Physical unclonable functions (PUFs) is threatened by the state change of the power-up value (R) at different temperatures. The voltage ramp-up time Tramp is one of the factors that can affect the stability of R. Some studies have been performed on the Tramp of commercial SRAM chips at the microsecond (μs) level. In this paper, a robust and low cost SRAM PUF using a p-channel metal oxide semiconductor (PMOS) as a power switch to enhance the stability of R is proposed. Tramp is as fast as 11 V/ns. The proposed SRAM PUF has a linear shift register extractor, with an extraction rate as high as 7/18 and no helper data in contrast to traditional von Neumann extractor. This chip has been fabricated using 0.11 μm ultra-low-leakage technology. The experiment results show that R becomes stable at [-40 °C, 85 °C], and a simple lightweight error correcting codes (ECC) can be used in SRAM PUF.

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication’s process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for ‘1’) or low resistance state (for ‘0’), according to the customized ring oscillator (RO) true random number generator’s digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of $1.82~\mu \text{m}^{2}$ (i.e., 108 $F^{2}$ ), which is capable of generating ~107 PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG’ dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by $5.36\times $ and the BER per 10°C is improved by $4\times $ , even under the widest operating temperature range from −50°C to 150°C.

Physically unclonable functions based on small delay defects in QCA

Physically unclonable functions (PUFs) as a physical security entity are widely used in conventional CMOS technology. The specific structure of circuits in quantum dot cellular automata (QCA) technology does not allow the use of the same techniques of CMOS to effectively applied for implementation of PUF in QCA. However, the QCA technology is much susceptible to various random fabrication defects. A large group of these defects is small delay defects (SDDs) that cannot cause a fault at the nominal conditions. In this paper, we propose a PUF construction based on SDDs as a physical feature of QCA technology. For simulation, we randomly inject defects in a circuit, particularly the majority voter gates in an arithmetic unit. A set of picked challenges is applied to the circuit to excite SDDs. The existence of SDDs is disclosed using a new delay-based model that also converts the size of defect to a bit string. Finally a collection of bit strings corresponding to the size of SDDs forms the PUF response or the signature of the entity. The results of simulations exhibit the benefit of SDDs for the realization of PUF in QCA. The extracted signatures satisfy the required robustness and security measures for the PUF objectives such as identification.