Physical Unclonable Function Circuit Research Articles

Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT

Remote integrity verification plays a paramount role in resource-constraint devices owing to emerging applications such as Internet-of-Things (IoT), smart homes, e-health, and so on. The concept of Virtual Proof of Reality (VPoR) proposed by Rührmair et al. in 2015 has come up with a Sense-Prove-Validate framework for integrity checking of abundant data generated from billions of connected sensors. It leverages the unreliability factor of Physically Unclonable Functions (PUFs) with respect to ambient parameter variations such as temperature, supply voltages, and so on, and claims to prove the authenticity of the sensor data without using any explicit keys. The state-of-the-art authenticated sensing protocols majorly lack in limited authentications and huge storage overhead. These protocols also assume that the behaviour of the PUF instances varies unpredictably for different levels of ambient factors, which in turn makes them hard to go beyond the theoretical concept. We address these issues in this work 1 and propose a Machine Learning (ML) assisted PUF calibration scheme to predict the Challenge-Response Pair (CRP) behaviour of a PUF instance in a specific environment, given the CRP behaviour in a pivot environment. Here, we present a new class of authenticated sensing protocols where we leverage the beneficence of ML techniques to validate the authenticity and integrity of sensor data over ambient factor variations. The scheme also reduces the storage complexity of the verifier from O ( p * K * l * ( c + r )) to O ( p * l *( c + r )), where p is the number of PUF instances deployed in the framework, l is the number of challenge-response pairs used for authentication, c is the bit lengths of the challenge, r is the response bits of the PUF, and K is the number of levels of ambient factor variations. The scheme alleviates the issue of limited authentication as well, whereby every CRP is used only once for authentication and then deleted from the database. To validate the proposed protocol through actual experiments on FPGA, we propose 5-4 Double Arbiter PUF, which is an extension of Double Arbiter PUFs (DAPUFs) as this design is more suited for FPGA, and implement it on Xilinx Artix-7 FPGAs. We characterise the proposed PUF instance from −20° C to 80° C and use Random Forest --based ML technique to generate a soft model of the PUF instance. This model is further used by the verifier to authenticate the actual PUF circuit. According to the FPGA-based validation, the proposed protocol with DAPUF can be effectively used to authenticate sensor devices across wide variations of temperature values.

A Strong Physically Unclonable Function With >2⁸⁰ CRPs and <1.4% BER Using Passive ReRAM Technology

We experimentally demonstrate a strong physically unclonable function (PUF) circuit featuring >280 challenge-response pair (CRP) capacity, ${F }= 250$ -nm half-pitch $64\times 64$ ReRAM circuits. Passive crossbar circuits with $4{F} ^{2}$ area per crosspoint device and reduced peripheral overhead, not requiring any circuitry for programming, result in an extremely compact design, while low-power consumption is achieved by keeping ReRAM devices in the highly resistive, virgin states. The key contributions of this letter is a novel leakage injection approach using an electrically isolated portion of the crossbar array, which boosts PUF’s robustness, and a key-booking scheme, which dramatically improves reliability across a wide temperature range of operation and further increases PUF circuit density by reducing error correcting overheads. The experimental results showed near-ideal functional performance metrics, including 49.55% uniformity, 49.95% diffuseness, and 49.25% uniqueness. The measured response also passed all relevant NIST randomness tests.

A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test

Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits. However, its FPGA implementation has a poor reliability, and error correction codes (ECCs) are usually needed to eliminate the noise in the responses, which incur additional high hardware overhead and require NVM for helper data storage. In this paper, we present a highly reliable arbiter PUF with improved uniqueness using the bit-self-test (BST) strategy. A delay detection circuit is added into a classical arbiter PUF to test the delay deviation that produces each bit of the PUF response in real-time and mark the response as reliable using a reliability flag when the delay deviation is significantly more than a predefined threshold. Then, the robust responses can be used. We implemented the BST-arbiter PUF on a Xilinx Artix 7 FPGA. The test results show that the selected responses achieve outstanding performance where the bit error rate is less than 10−9, the bias is 50.3%, and the uniqueness is 49.1%. Thus, the BST-APUF, which drastically reduced the ECC overhead, can be applied to lightweight cryptography applications.

Impact of Scaling on Physical Unclonable Function Based on Spin–Orbit Torque

We analyze the scalability of a spin–orbit torque random access memory (SOT-MRAM)-based physical unclonable function (PUF) at the nanoscale size by means of a hybrid CMOS/spintronics simulation framework. The properties of the SOT-MRAM device (diameters from 100 nm down to 25 nm) are computed via micromagnetic simulations, whereas their implications for PUF applications are evaluated at the circuit level in terms of energy characteristics and security metrics. Obtained results prove that the implementation of 2 b xor operations in the designed PUF circuit achieves randomness and uniqueness very close to the ideality.

Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function

A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.

A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS

This paper presents a physically unclonable function (PUF) based on the randomness of soft gate oxide breakdown (BD) locations in MOSFETs, namely, soft-BD PUF. The proposed PUF circuit features a self-limiting mechanism that generates exactly one soft-BD spot in a pair of NMOS transistors. Highly stable “0” and “1” bits with an equal probability of 0.5 are extracted based on the locations of the generated BDs. A differential readout scheme is employed based on the proposed reference-free sense amplifier (SA), resulting in good current sensitivity and side-channel attack resilience. The soft-BD PUF, fabricated in a 40-nm CMOS process, comprises all essential periphery circuits. Measurements show that the soft-BD PUF has good data stability in a wide operating range. The native bit error rate is 0% for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V and above, shown by measuring 10k readout cycles among 10k PUF cells. Data stability degrades at lower supply voltage and higher temperature due to the conductivity of PUF cells and the offset of SAs. Under the nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 0.9 V in this technology, the throughput is shown to be at least 40 Mb/s and the PUF readout consumes only 51.8 fJ/bit. The averaged hamming weight and hamming distance are 0.497 and 0.496, respectively, showing a good randomness and uniqueness. The resulting PUF data show good statistical properties by passing all the relevant tests in the NIST 800-22 suite.

PbS Quantum Dots Based on Physically Unclonable Function for Ultra High-Density Key Generation

Secure data encryption depends on the one-way functions and copy protection relies on features that are hard to reproduce. Herein, we present the physically unclonable function (PUF) concept based on PbS quantum dots (QDS) for ultra high-density key generation. Compared with existing PUFs, the proposed QDs-based PUF may boost the key density by about an order of magnitude, and also has certain advantages in terms of uniqueness, randomness and spatial characteristics. The proposed PUF passes applicable National Institute of Standards and Technology randomness tests. The area/bit is 14.5 nm2 for PbS QDs-based PUF1, 54.76 nm2 for PbS QDs-based PUF2, respectively. Compared with optical PUF, it improves the key density about 9.6 times and 2.3 times, respectively. Further, PbS QDs-based PUF1 and PbS QDs-based PUF2 demonstrate the larger data spaces and the read data has better spatial characteristics and uniqueness. We anticipate the QDs-based PUF circuit would shed light on future research of circuit design and information security technology.

A 0.1-pJ/b and ACF &lt;0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins’ cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm2 with a 4.9- $\mu \text{m}^{2}$ bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks.

A PUF-based unified identity verification framework for secure IoT hardware via device authentication

In the era of Internet-of-Things (IoTs), millions of smart devices are interconnected and communicated through networks. To guarantee the security and reliability of data transmission in IoT, the underlying hardware of these devices must first be secure and trusted. However, due to the inherent mobility nature of current embedded devices, IoT hardware could be vulnerable to diverse security threats from multiple malicious participants. Among them, device theft is becoming one of the most challenging security issues that have incurred a serious impact on copyright. To effectively alleviate this threat, silicon physical unclonable function (PUF) has been presented and considered to be a reliable anti-piracy solution to complete the device authentication and key storage. However, current PUF solutions are mostly focused on chip-level verification and cannot provide systematic identification and authentication. To this end, this article proposes a unified identity verification framework which can provide fine-grained protection for embedded devices against theft attacks from the system level. This framework is established on a series of PUF circuits that have been implanted into each individual chip of the devices. We first improve the configurable ring oscillator (CRO) PUFs with the latch structure. Therefore, a unique sub-digital signature of each chip can be generated by performing the challenge-response strategy. We then reassemble all the sub-digital signatures and encode them to acquire the unique fingerprint of each embedded device, so as to achieve system-level device identification and authentication. Any substitution of an individual or all chips in the devices will result in the inconsistencies of the system-level fingerprint. We implement and verify the proposed scheme on the field programmable gate array (FPGA) platforms. Experimental results illustrate that the proposed framework can uniquely and accurately identify any or all of the thefts to the embedded system hardware at low silicon overhead.

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

With rapid advances in edge computing and the Internet of Things, the security of low-layer hardware devices attract more and more attention. As an ideal hardware solution, field programmable gate array (FPGA) becomes a mainstream technology to design a complex system. The designed modules are named as intellectual property (IP) cores. In this paper, we consider both misappropriation of hardware devices and software IPs in edge computing and propose a PUF-based IP copyright anonymous authentication scheme. The scheme utilizes the double physical unclonable function (PUF) authentication model. Both the parties generate the challenge jointly in authentication to avoid replay attack and modeling attack on PUF circuit. The complexity of authentication is greatly reduced. Besides, the server of FPGA vendor is unnecessary to store all the challenge response pairs (CRPs) of each PUF-based chip due to the use of the double PUF authentication model. It saves the system resource and achieves better security. To protect software IP, IP core vendor inserts copyright information and anonymous buyer identity information into the design before trading. The anonymity of the buyer ensures the benefits of the buyer. With the participation of trustable device vendor, infringement behavior can be traced according to extracted fingerprints. The experiments show that the resource overhead of the proposed scheme is reduced by 61.96% and 31.61% by comparing with 2-1 DAPUF and built-in self-adjustable PUF. Besides, PUF stability is 99.54%. It demonstrates the good performance of the proposed scheme.

Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs

Physical unclonable functions (PUFs) leveraging minute silicon process variations have been proposed for generating the device-tied secret keys. When creating the PUF-based keys, the high energy and area costs for implementing error corrections can far exceed the costs of the basic PUF circuits alone. It is critical to minimize the end-to-end cost of the reliable key generation; otherwise, the application of PUFs would be greatly limited. In this paper, we propose a new PUF scheme that uses a circuit with two different oscillation modes (bimodal oscillation) to realize the autonomous majority voting and improve PUF reliability. This design is novel and efficient because the voting procedure is realized with a self-timed oscillating circuit without orchestration by a clock signal. We use both circuit simulation and FPGA implementation to evaluate the reliability tradeoffs achieved by different parameterizations of the design, to show that the design performs well across a range of supply voltages, and to quantify the robustness of the design across a broad range of operating temperatures.

Highly Reliable Multiport PUF Circuit Based on MOSFET Zero Temperature Coefficient Point

By using processing variations in the unitcircuits of the same structures and design parameters during manufacturing, Physical unclonable function (PUF) generates security keys with characteristic of uniqueness, randomness and unclonability. In this paper, a highly reliable multiport PUF scheme was proposed based on MOSFET Zero temperature coefficient (ZTC) point. It consists of input register, deviation-current generating module, arbiter array and obfuscation circuit. After reconfiguring deviation-current generating module by applying different input challenges, the PUF circuit updates keys without physical replacement. And multi-bit keys can be generated in one clock cycle. In TSMC-LP 65nm CMOS technology, the layout of 64-port reconfigurable PUF occupies 131μm×242μm with custom designing. Experimental results show that the PUF circuit has good statistical characteristic of uniqueness and randomness. It exhibits high reliability of 98.2% with respect to temperature variation from -40°C to 125°C and supply voltage variation from 1.08V to 1.32V, indicating that it can be reliably and effectively used in information security field.

A Reliable Strong PUF Based on Switched-Capacitor Circuit

This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge–response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by an SC circuit and further amplified by a latch-styled sense amplifier. By covering the entire chip with the metallic transmission lines connected to the sampling capacitor, the PUF can resist invasive attacks. To provide highly reliable responses, a built-in self-test (BIST) strategy is also adopted. A test capacitor is embedded in the PUF circuits to automatically test the capacitance deviation of the SC circuit. Only when the capacitance deviation is large, the output of the PUF is selected for use. The proposed strong SC PUF circuit is fabricated and verified using HJ standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that after using the BIST strategy, the bit error rate is less than $10^{-9}$ when the ratio of the selected responses is 19.6% for the PUF instances in our test.

A framework to enhance security of physically unclonable functions using chaotic circuits

As a new technique for authentication and key generation, physically unclonable function (PUF) has attracted considerable attentions, with extensive research results achieved already. To resist the popular machine learning modeling attacks, a framework to enhance the security of PUFs is proposed. The basic idea is to combine PUFs with a chaotic system of which the response is highly sensitive to initial conditions. For this framework, a specific construction which combines the common arbiter PUF circuit, a converter, and the Chua's circuit is given to implement a more secure PUF. Simulation experiments are presented to further validate the framework. Finally, some practical suggestions for the framework and specific construction are also discussed.

A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions

Physically unclonable functions (PUFs) are one of the most important breakthrough for security of devices as they represent a low-cost means to provide authentication and secure storage. PUFs measure nano-scale mismatches that are inherently caused by the manufacturing process. However, the mechanisms exploited by PUF circuits depend on the working conditions, such as temperature, device aging, and current flow, making them unreliable and, hence preventing their wider employment. One of the most investigated PUF exploits pairs of ring oscillators (ROs): frequencies measured from each pair are compared for extracting one response bit. However, extracted bit-strings are not suitable for authentication purposes as they may change during time. In this paper, we propose a new identification mechanism, based on ROs, which is immune to aging and working conditions. Through a mathematical demonstration and an extensive experimental campaign, which involved real field programmable gate array devices, we demonstrate its ability to reliably accomplish identification of silicon devices.

True random number generator based on ring oscillator PUF circuit

In this paper we propose the method of generating true random numbers utilizing the circuit primarily designed as Physically Unclonable Function (PUF) based on ring oscillators. The goal is to show that it is possible to design the universal crypto system, that can be used for various applications – the PUF can be utilized for asymmetric cryptography and generating asymmetric keys, True Random Number Generator (TRNG) for symmetric cryptography (generating session and ephemeral keys), nonces and salts. In the paper the results of evaluation of such a circuit utilized for TRNG purpose are presented.

Robustness Analysis of a Memristive Crossbar PUF Against Modeling Attacks

In the greater context of computer security, hardware security issues such as integrated circuit counterfeiting, cloning, reverse engineering and piracy have emerged as critical issues due in part to an increasingly globalized supply chain. To help combat hardware security vulnerabilities, a wide range of security primitives have emerged in recent years. A popular example is physical unclonable functions (PUFs) that leverage process variations to provide unique signatures or fingerprints that can be used for authentication or secret key generation. Nanoelectronic technologies, such as the memristor technologies considered here, provide an excellent opportunity to engineer dense, energy-efficient PUF circuits with desirable statistical properties. Here, we specifically focus on the design considerations of a memristive crossbar based PUF that generates response bits as a function of variable memristor switching time. In addition to describing the operation of the crossbar PUF, we also consider its resilience to two specific machine learning attacks, specifically through the use of linear regression and support vector machines. Two circuit design modifications for the crossbar PUF are provided to improve the resilience to machine learning attacks: XORing of response bits and internal column swapping. We show that the design modifications lead to a reduction in the likelihood of successful attack to about 50% (near ideal) even given 5000 iterations for the attack itself. We also provide power estimates and performance considerations for the crossbar PUF based on three specific memristive material stacks: hafnium-oxide, tantalum-oxide, and titanium-oxide.

A novel current controlled configurable RO PUF with improved security metrics

Physical Unclonable Functions (PUFs) are promising hardware security primitives which produce unique signatures. Out of several delay based PUF circuits, Configurable Ring Oscillator (CRO) PUF has got higher uniqueness and it is resilient against modelling attacks. In this paper, we present a novel Current controlled CRO (C-CRO) PUF in which inverters of RO uses different logic styles: static CMOS and Feedthrough logic (FTL). Use of different logic styles facilitates improvement of security metrics of PUF. The analysis of security metrics of the proposed architecture is carried out in 90nm CMOS technology shows, using FTL logic leads to better security metrics. Proposed C-CRO PUF is also both power and area efficient. Further, in order to measure the vulnerability of proposed PUF, machine learning attack is carried out and the result shows FTL RO based C-CRO PUF is highly resilient to machine learning attack because of its non-linearity property.

PUF‐based encryption method for IC cards on‐chip memories

This Letter presents a self-controlled physical unclonable function (PUF) circuit and its application in encrypting on-chip memories of IC bank cards. The PUF circuit is based on cross-coupled NAND gates. Voting and Hamming code address the stability of its outputs. The Monte Carlo simulation and field-programmable gate array board are used for verification. The Voting method improves the error rate 79%. The Hamming codes and convertor can correct every error bits of PUF outputs. The PUF outputs, data address and time-stamp are encrypted by SM4 (Chinese block cipher algorithm standard) to generate KEY. The data does XOR with the KEY.