Physical MOSFET Model Research Articles

Dynamic data retention and implied design criteria for floating-body SOI DRAM

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications.

IIIB-3 a unified analytical physical MOSFET model

IIIB-3 a unified analytical physical MOSFET model

Small-signal MOSFET one-dimensional admittance model

A small-signal a.c. admittance ( y-parameter) circuit model is developed by physical analysis of the basic MOSFET structure by using a small signal analysis. The frequency dependent solutions for the derived set of equations for the y-parameters yield results that match experimental data extremely well. The real parts of the y-parameters vary as ω 2, while the imaginary parts vary linearly. In carrying out the analysis it was necessary to add parasitic elements to the physical MOSFET model as well as include the effects of channel length modulation. The y-parameters are expressed as a function of the MOSFET parameters, parasitic elements, frequency and bias conditions.