Physical Design Level Research Articles

Resource Management Solutions for Modern Law Firms: A Comprehensive Database

In the modern legal landscape, resource management plays a crucial role in the sustained development of law firms and in delivering high-quality legal services to clients. However, there are still law firms that have deviated from database technology and continue to rely on traditional resource management models, which cannot meet the needs of modern enterprise management. This paper aims to explore the current status of resource management in law firms and introduces the design of a universal resource database tailored to the needs of law firms, lawyers, and clients. This paper provides a detailed introduction to the design of the comprehensive resource management database from the perspectives of requirement analysis, conceptual level design, logical level design and physical level design. The comprehensive database primarily store data related to staffs, orders, and clients, providing efficient resource management, and allowing for further expansion on this foundation. Effective resource management is paramount for law firms to maintain their competitiveness and provide excellent legal services, ultimately enhancing the overall client experience.

Electromigration-Aware Architecture for Modern Microprocessors

Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden on the VLSI implementation flow because they impose severe physical constraints. This paper focuses on electromigration (EM), one of the critical factors affecting semiconductor reliability. EM is the aging process of on-die wires in integrated circuits (ICs). Traditionally, EM issues have been handled at the physical design level, which enforces reliability rules using worst-case scenario analysis to detect and solve violations. In this paper, we offer solutions that exploit architectural characteristics to reduce EM impact. The use of architectural methods can simplify EM solutions, and such methods can be incorporated with standard physical-design-based solutions to enhance current methods. Our comprehensive physical simulation results show that, with minimal area, power, and performance overhead, the proposed solution can relax EM design efforts and significantly extend a microprocessor’s lifetime.

Area efficient camouflaging technique for securing IC reverse engineering.

Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit's reverse engineering. An attacker may not identify various logic gates in the layout due to similar image output. In addition, a dummy or true contact-based technique is implemented for optimum outcomes. A library of gates is proposed that contains the various camouflaged primitive gates developed by a combination of using the metal routing technique along with the dummy contact technique. This work shows the superiority of the proposed technique's performance matrix with those of existing works regarding resource burden, area, and delay. The proposed library is expected to make open source to help ASIC designers secure IC design and save colossal revenue loss.

Rapid Prototyping of Inertial MEMS Devices through Structural Optimization.

In this paper, we propose a novel design and optimization environment for inertial MEMS devices based on a computationally efficient schematization of the structure at the a device level. This allows us to obtain a flexible and efficient design optimization tool, particularly useful for rapid device prototyping. The presented design environment—feMEMSlite—handles the parametric generation of the structure geometry, the simulation of its dynamic behavior, and a gradient-based layout optimization. The methodology addresses the design of general inertial MEMS devices employing suspended proof masses, in which the focus is typically on the dynamics associated with the first vibration modes. In particular, the proposed design tool is tested on a triaxial beating-heart MEMS gyroscope, an industrially relevant and adequately complex example. The sensor layout is schematized by treating the proof masses as rigid bodies, discretizing flexural springs by Timoshenko beam finite elements, and accounting for electrostatic softening effects by additional negative spring constants. The MEMS device is then optimized according to two possible formulations of the optimization problem, including typical design requirements from the MEMS industry, with particular focus on the tuning of the structural eigenfrequencies and on the maximization of the response to external angular rates. The validity of the proposed approach is then assessed through a comparison with full FEM schematizations: rapidly prototyped layouts at the device level show a good performance when simulated with more complex models and therefore require only minor adjustments to accomplish the subsequent physical-level design.

Low power synthesis for asynchronous FIFO using unified power format (UPF)

Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

NanoMagnet logic (NML) is among the emerging technologies that might replace CMOS in the next decades. According to its physical characteristics, to better exploit the potential of this technology—and of other similar ones—the use of parallel architectures with regular layout that avoid long interconnection signals is advised. Systolic arrays (SAs) are among these architectures, being composed of a grid of equal processing elements that are locally interconnected. However, they are usually implemented to execute only a small set of algorithms, and for this reason, throughout the years, they have not been an appealing solution for CMOS. To seriously analyze the potentials of NML, complex architectures must be conceived, and their physical implementation explored considering realistic technological constraints. With the increasing complexity of NML circuits, two issues, then, are noticed: 1) the need for a regular structure arises, that at the same time helps to reduce the intrinsic pipelining nature of NML and can be configured to be used for several applications without developing a dedicated design for each algorithm and 2) the capability to synthesize, place and route NML circuits is fundamental to demonstrate the feasibility of the architecture in two important conditions: efficiently managing the complexity of the design and sticking to the characteristics that are technologically feasible at the time of writing. In this paper, we address these issues presenting a new reconfigurable SA that can be programmed to execute different algorithms, and we provide two examples to show its working principle. Moreover, the array is synthesized and simulated with the aid of the first real tool for nanotechnology circuits that we have conceived, Torino Politecnico Nanotechnology tool. The joint contribution at both the architectural and physical design levels gives a relevant step forward to the state of the art in the demonstration of this emerging technology potential.

Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors

Radiation induced faults in digital systems have started gathering major attention in recent years due to increasing reliability concern for future technologies. For future technologies, multiple transient faults (MTF) originating from a single radiation hit are expected to occur more frequently. Further, due to continuous massive scaling in device geometry, a particle with moderate linear energy transfer (LET) values is expected to affect more than one module/device during striking. Additionally, incessant escalation in operating speed with evolution of technology has increased likelihood of multi-cycle transient (MCT) faults in digital circuits. This calls for novel solutions for concurrently tackling multi-cycle transient and multi-transient fault resiliency at a higher design abstraction level such as behavioral level. This paper proposes a novel approach for generating simultaneous multi-cycle transient and multiple transient fault resilient designs during high level synthesis (HLS) of application specific datapath processors using the framework of dual modular redundancy. Results of the proposed approach on benchmarks indicated generation of low cost MCT–MFT resilient designs during HLS within acceptable runtime.

Efficiently Exploring FPGA Design Space Based on Semi‐Supervised Learning

Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.

A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust

During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the fields of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background effects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background effects leads to a better Trojan-to-background-effect ratio and more (by about 1.7 times) Trojan detectability.

Thermal Pathfinding for 3-D ICs

System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack.

Review of the State of Art of Tunable Impulse Ultra-Wideband Technology as Integrator for Wireless Sensing and Identifications Short-Range Networks

Impulse based Ultra wideband technology has been the motivation of many recent researches with the potential of many applications to be researched. The uniqueness of the physical characteristics of the generated signal combined with the high flexibility of for different data rates at the physical layer design level have been addressed in considerable number of researches recently. This paper presents in depth reviews of the different concepts of tunable impulse based ultra wideband from the different researchers views. Research proposals of Cross layer architectures as PHY-MAC aware Impulse based ultra wideband solutions, link-budget communication design with performance evaluations in different test beds implementations are investigated in this paper. Such in-depth review can help researchers in this field to have better understanding of the different possibilities of designing new impulse-based ultra wideband solutions for future potential communication scenarios. Special focus on utilizing the advantage of impulse-based ultra wideband signal design flexibility as integrator for different short to medium wireless infrastructures mainly sharing common design constraints and requirements. Finding remarks from reviewing nearest-field literature combined with researches benchmarking to inspire researches proposal for this topic.

Networked Labs-on-a-Chip (NLoC): Introducing networking technologies in microfluidic systems

Microfluidics is a science and a technology which deals with manipulation and control of small volumes of fluids flowing in channels of micro-scale size. It is currently used for Labs-On-a-Chip (LoCs) applications mainly. In this context, recently fluids have been used in the discrete form of droplets or bubbles dispersed into another immiscible fluid. In this case, droplets or bubbles can be exploited as a means to transport digital information between microfluidic components, with sequences of particles (i.e. droplets or bubbles) representing sequences of binary values.LoCs are today realized through monolithic devices in which samples are processed by passing them through a predetermined sequence of elements connected by fixed and preconfigured microfluidic channels. To increase the reusability of LoCs, effectiveness and flexibility, networking functionalities can be introduced so that the sequence of elements involved in the processing can be dynamically selected. Accordingly, in this paper we introduce the Networked LoC (NLoC) paradigm that brings networking concepts and solutions into microfluidic systems such as LoCs. More specifically, in this paper the need for the introduction of the NLoC paradigm is motivated, its required functions are identified, a system architecture is proposed, and the related physical level design aspects, such as channel characterization, information representation and information capacity are investigated.

Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for Through Silicon Via

This paper presents the physical level design analysis of 3D stacked memory ICs with Through Silicon Via (TSV) to compute the propagation delay. The difficulties in incorporating TSVs for 3D ICs are that TSV has additional complex parasitics, process based variations, and structure based reliability issues, thus warranting detailed modeling and analysis. TSVs are known to have a MOS structure which has been rigorously studied to evaluate the overall TSV performance and the effect of variable wafer doping profiles has been included in our analysis. Our proposed TSV model provides the IC designer with the yardstick for optimum TSV pitch. Furthermore, our model considers the TSVs to have a variable capacitor which enables frequency selective characteristics based on signal strength and operating frequency. Finally, we have incorporated our model towards optimization of memory array size in 3D stacked DRAMs while taking into account the key factors of TSV delay for a given process node and TSV pitch. This exhaustive analysis would help to choose optimum memory array size while stacking, without degradation in overall 3D Dynamic Random Access Memory (DRAM) performance, and can be effectively used as a primary guideline during memory stacking and layout for optimum bandwidth.

Complete Circuit Level Random Variation Models of Nanoscale MOS Performance

In this research, the complete analytical circuit level models of random variations in large and small signal parameters of any nanoscale MOS transistor have been proposed. Both triode and saturation regions have been explored. This research has been performed based upon the up to dated nanoscale regime MOS equations with the inclusion of all leading sources of variations instead of only threshold voltage variation. The proposed models have been verified at the nanometer level by using the Monte Carlo SPICE simulations and the Kolmogorov-Smirnof goodness of fit tests. These models are very accurate since they can fit the Monte Carlo based distribution with as high as 99% confidence. Obviously, they eliminate the gap between the circuit level and physical level design since the mismatches in the circuit level parameters can be now analytically formulated in terms of the physical level ones. So, the physical level causes and their relationships with the resulting circuit level mismatches can be revealed. Beside, the proposed models can also be expected to be the potential mathematical foundations for implementating the Electronic CAD cell libraries of the nanoscale MOS transistors. Hence, these models have been found to be efficient for the statistical/variability aware design of various CMOS analog/mixed signal circuits and systems in the nanoscale regime.

All Systems Go

This paper discussed about Alberto Sangiovanni-Vincentelli who has been one of the most influential innovators in the domain of electronic design automation (EDA) over the past 40 years. It is hard to find any topic in the field to which he has not contributed in one form or another. Yet over the past decade his attention has been uniquely and passionately devoted to the conception and realization of a methodology called platformbased design (PBD). The premise of PBD is to bring to system-level design the same mathematical rigor and structured design philosophy that has been so successful at the physical and logic design levels. Or-as Alberto stated very succinctly in his keynote at CDNLife! in 2007-to transform the field of system-level design from an art into a science.

An MTCMOS technology for low-power physical design

Multi-threshold CMOS (MTCMOS) technology is an effective sub-threshold leakage power reduction method in CMOS circuits, which satisfies high-performance and low-power design requirements. The optimization of virtual supply network plays an important role in MTCMOS low-power design. Existing low-power works are mainly on gate level, without any optimization on physical design level, which can lead to a large amount of virtual supply networks. Merging the objective of virtual networks minimization into physical design, this paper presents (1) a low-power-driven physical design flow; (2) a novel low-power placement to simultaneously place standard cells and sleep transistors; and (3) the sleep transistor relocation technique to further reduce the virtual supply networks. Experimental results are promising for both achieving up to 28.15% savings for virtual supply networks and well controlling the increase of signal nets.

Unified Incremental Physical-Level and High-Level Synthesis

Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level design-automation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72times and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-level-synthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.

Predicting potential performance for digital circuits

Presents a new concept of potential slack to measure so-called potential performance of digital circuits. Potential means how much improvement could be made in the future in terms of timing, area, and power dissipation. Predicting potential performance helps the circuit designers make good design decisions at a specific level of abstraction. The authors describe two algorithms for potential slack: an optimal algorithm and a fast greedy algorithm. The former is based on a maximal-independent set on transitive graphs, while the latter focuses on potential slack estimation in a greedy manner. Applications to gate- and physical-level design problems are provided to show the effectiveness of potential slack in predicting the potential performance of digital circuits.

Abstracting and Exploring Functional Design Information for Conceptual Mechanical Product Design

The conceptual stage of mechanical product design has been recognised as the most critical product development stage. This is an area which is not addressed by current CAD systems. In this paper, we present our work on the abstraction and exploration of functional design information to support this design area. We consider the exploration of relevant functional design information as an important aspect of design work during this design process. Four aspects of functional design information are abstracted, including function, behaviour, structure and working environment. The working environment information is demonstrated as being useful to the exploration of functional design solutions. The physical behaviour is represented by an input-output flow-of-action, contrary to the commonly-used input-output flow-of-object approach (where object refers to material, energy or signal). Not only is this approach more generic, more importantly, we argue that the input-output flow-of-object is only a physical-level design abstraction, while flow-of-action is a functional-level design abstraction, hence it can capture design intention. Based on this strategy, we explore functional design information by considering the relevant action flows between the design and its working environment, as well as between the different components of the design, including their attributes, attribute expressions, constraints, and so on. Prototype software has been developed to implement the proposed approaches. A simple design example is used to illustrate the various aspects of functional design information and their exploration process.