Abstract
Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit's reverse engineering. An attacker may not identify various logic gates in the layout due to similar image output. In addition, a dummy or true contact-based technique is implemented for optimum outcomes. A library of gates is proposed that contains the various camouflaged primitive gates developed by a combination of using the metal routing technique along with the dummy contact technique. This work shows the superiority of the proposed technique's performance matrix with those of existing works regarding resource burden, area, and delay. The proposed library is expected to make open source to help ASIC designers secure IC design and save colossal revenue loss.
Highlights
Reverse engineering (RE) is one of the primary concerns and long-standing problems to governments, militaries, and industries all over the world [1]
This paper focuses on research based on area efficient camouflaging techniques and the development of a library of camouflaged primitive logic gates using the said technique for application specific Integrated Circuit (IC) (ASIC) designers
The proposed method rests on designing logic gates by implementing layout techniques and developing an open-source standard cell library so that application-specific integrated circuit (ASIC) designers can use this library for designing chips
Summary
Reverse engineering (RE) is one of the primary concerns and long-standing problems to governments, militaries, and industries all over the world [1]. It covers objects from as large as aircraft down to the smallest Integrated Circuit (IC), through which an object is examined to gather a complete understanding of its construction and/or functionality It is recognized worldwide and has many noble purposes: failure analysis and defect identification, detection of counterfeit products, recovery of manufacturing defects, Confirmation of Intellectual property, Hardware Trojan detection, education, and research, etc. Reverse engineering attacks recover the original netlist through scanning electron microscopy (SEM) images [14, 15] It is usually applied in combinational logic of an application-specific integrated circuit (ASIC) and proactively hides the layout information of intellectual properties (IPs), intending to make RE exponentially more difficult [16]. This paper focuses on research based on area efficient camouflaging techniques and the development of a library of camouflaged primitive logic gates using the said technique for application specific IC (ASIC) designers
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