Photoresist Coverage Research Articles

Electromigration in sintered nanoporous copper

The current feed capacity of electrical interconnects is mainly limited by the poor electromigration (EM) resistance of lead free-solder interconnects. Thus, the community investigates alternative interconnect approaches and materials, e.g. all-copper interconnects using copper pastes. EM is an electron scattering based transport of metal atoms, occurring at high current densities, resulting in voids and thus finally leads to an open interconnect. For all-copper interconnects, it is expected that the maximum current density could be increased, while power losses can be mitigated, due to the higher EM resistance and reduced resistivity of copper compared to solder, respectively. However, all-copper interconnects formed by copper pastes applied without pressure result in a porous copper interconnect morphology with unknown EM performance. Thus, the authors report on results of EM tests on nanoporous copper films. The investigated copper paste is especially designed to be used for flip chip interconnects and contains nano and micron sized copper particles. Paste films were performed by doctor blading, followed by a sintering process at 200°C in formic acid. SEM analysis on FIB cross-sections of sintered films revealed the fusion of the nanoparticles to a nanoporous, sponge like morphology with embedded microparticles. Furthermore, a porosity of approximately 30% could be identified. The high porosity results in a non deterministic electrical network with a measured effective resistivity of ~10 μΩ cm, which is five times higher than the one of bulk copper (1.78 μΩ cm). For detailed investigations of the EM characteristics a setup, as well as a specific test sample layout were designed and implemented. The setup is capable to feed a current of up to 40 A to eight serial samples in a temperature range from room temperature to 250°C in ambient atmosphere. The test samples consist of copper lines, relief printed onto a silicon based carrier substrate, to bridge a 200 μm wide gap between two electrochemically deposited copper electrodes. The voltage drop across the copper line can be measured while driving the current through the line, by four point probing. In addition, a platinum based thermocouple (PT1000) is implemented on the carrier substrate beneath the nanoporous copper. It allows to prove the temperature of the nanoporous copper, to derive exact test conditions and the temperature coefficient of resistance of the nanoporous copper. Initial tests of samples exposed to elevated temperatures above 90°C, but without any current applied, resulted in the resistance increase of the nanoporous copper due to oxidation. Accordingly, a photoresist coverage was applied on the copper lines to mitigate the copper oxidation to levels acceptable for EM testing. A series of EM tests were then performed under constant current conditions to derive the EM kinetics and to explore the damage mechanisms. At current densities of 1 MA/cm^2 and a sample temperature of 90°C, the observed ‘time to failure’ of the nanoporous copper was more than six times higher than the one of tin based lead free solder. Furthermore, the authors will summarize their findings of the EM study performed on the nanoporous copper.

Surface tension/thermal mismatch in a self-assembly process

Surface tension is increasingly used for the self-assembly of 3D microstructures. This paper studies the use of a benzocyclobutene (BCB) photo-resist material for the out-of-plane rotation via self-assembly behavior of a silicon micro-part. The literature discusses both surface-tension self-assembly and thermal-mismatch self-assembly, but these two topics are treated separately. Due to its relatively large thermal expansion coefficient, the BCB photo-resist material exhibits both surface-tension and thermal-mismatch effects during self-assembly. Therefore, the residual stresses induced by the self-assembly process on the interface between the melting pad and the microstructure are an issue that needs clarification. In order to quantify the shear stress on the interface, a micro-cantilever test specimen is designed and fabricated by a two-mask self-assembly process using a BSOI wafer and DRIE etching. Two cantilever designs are compared, one having a single section of photo-resist coverage and the other having two sections of photo-resist coverage. The MSC/NASTRAN finite-element method with an interfacial shear-lag model is used to estimate the deflection of the cantilever beam due to residual stresses from surface tension and thermal shrinkage. A clamped-edge-body-rotation model is proposed in order to calibrate measurement results by confocal optical microscopy with numerical results. The interfacial shear between the BCB photo-resist and the silicon structure is found to range from 0.4 to 1.0 MPa due to thermal shrinkage (after soft bake and structure release). The residual stress from surface tension (after material reflow and self-assembly) depends on the thickness of the PR layer and in some cases is twice the residual stress from material mismatch. Finally, a micro-mirror design employing BCB melting pads is presented to verify a self-assembly process powered by both surface tension and thermal mismatch.

Picoliter droplets for spinless photoresist deposition

In this article, we present an acoustically actuated two-dimensional (2D) micromachined ejector array for a zero waste and spinless droplet-by-droplet photoresist deposition method. The theory of operation, the experimental results obtained with acoustic focused 2D micromachined microdroplet ejector array is demonstrated. The ejector operation at 34.7MHz and generation of 21μm diam photoresist solvent droplets in drop-on-demand and continuous modes of operation are demonstrated. Photoresist droplets are ejected onto a wafer surface by this acoustic ejector array. Photoresist droplets are ejected on drop on demand and interact with each other by surface tension forces to generate photoresist coverage on the wafer surface during photoresist deposition by droplet generation. By overlapping ejected photoresist droplets, formation of a uniform thickness, line coverage is achieved. Multiple photoresist lines are printed simultaneously by a 3×3 ejector array. By overlapping photoresist lines, coverage of a 4in. silicon wafer with photoresist is achieved.

New photoresist coating method for 3-D structured wafers

This paper presents a method for the uniform coating with standard photoresist of a 〈100〉 semiconductor wafer containing anisotropically wet-etched through-holes. The coating method is based on photoresist dispensing on the mask opening side of the wafer and spinning the wafer from both sides in saturated photoresist solvent atmosphere. Special attention is paid to the improvement of photoresist coverage of the obtuse holes' corners by rounding them first in TMAH solution. The method offers the possibility for realisation of different structures in wafer through-holes. Moreover, it could also be applied for spinning photoresist in grooves with very good uniformity, which requires minimal changes in the standard coating equipment. The method is simple, fast and low-cost in comparison with other photoresist coating techniques.

Ion and neutral species in C2F6 and CHF3 dielectric etch discharges

Relative concentrations of reactive ions, neutral radicals, resist and substrate etch products have been measured in dielectric etch chemistries using an uncollided beam mass spectrometer/ion extractor from Hiden Analytical. Analysis techniques employed include both electron impact ionization and dissociative ionization of neutral gas, and potential bias extraction of positive ions from the reactor discharge volume. Measurements were made in C2F6 and CHF3 discharges in an inductively coupled plasma (GEC) research reactor operating with power densities, pressures, gas compositions and wafer materials typical of those found in etch processing tools. Wafer substrates investigated included blanket silicon wafers and silicon wafers with varying amounts of photoresist coverage of the surface (20%, 80% and 100%). In C2F6 discharges CF3+ was consistently the dominant fluorocarbon ion present, in agreement with published cross sections for dissociative ionization. Smaller concentrations of CF+, CF2+, and C2F5+, were also observed, though the dissociative ionization production of C2F5+ was a factor of 5 smaller than would be expected from published cross section values. The presence of photoresist, even in small amounts, was found to produce marked changes in the discharge composition. For example, in C2F6 discharges, concentrations of SiFx etch products relative to concentrations of CxFy species were notably diminished and larger concentrations of water vapor were observed when resist was present. In CHF3 discharges, CF3+ and CHF2+ were found to be the main species present, along with smaller concentrations of CF2+, CF+, CHF+, CH+ and F+.

Polysilicon gate etching in high density plasmas. IV. Comparison of photoresist and oxide masked polysilicon etching-thickness determination of gate oxide layers using x-ray photoelectron spectroscopy

The characteristics of oxide and photoresist masked polysilicon trench etching has been studied by real-time HeNe laser ellipsometry and quasi in situ x-ray photoelectron spectroscopy (XPS). Poly-Si films on SiO2-covered Si (100) substrates were masked either with a 1-μm-thick photoresist or a 200-nm-thick oxide hard mask. The 200-mm-diam wafers were etched downstream in a helicon high density plasma source using a chlorine-based gas chemistry. When using an oxide hard mask instead of a photoresist mask, the selectivity of polysilicon over oxide was improved by a factor greater than 3. A new approach to the surface characterization of semiconductor submicron structures by XPS is presented. Photoelectron signals originating from the gate oxide film and the underlying silicon substrate were measured in regular arrays of trenches. The ratio between the SiO2 peak area of the gate oxide film and the Si 2p peak area of the silicon substrate was correlated with the thickness of the SiO2 film. The thickness determined was obtained by calibrating peak area ratios with oxide thickness measurements using spectroscopic ellipsometry. Consequently, the gate oxide thicknesses derived from the area ratios were calculated in patterned areas after etching of photoresist and oxide hard masked polysilicon features as a function of the aspect ratio of the features and mask coverage on the wafer. It was found that the gate oxide consumption is enhanced in high aspect ratio features masked with photoresist as well as in areas with high photoresist coverage; the carbon coverage on the gate oxide film was found to scale with the increased gate oxide etching in the small features. Similar effects were not observed with the oxide masked sample.

Etching characteristics of tin oxide thin films in argon–chlorine radio frequency plasmas

We have developed an etch process suitable for high resolution transparent conductive oxide patterning with high etch rates, up to 70 nm/min, and applicability to large area flat panel display substrates. It was found that the addition of small amounts of Cl2 significantly enhanced the etch rate compared to addition of pure argon but that beyond 25% Cl2 the rate tended to fall. There is a significant loading effect where the etch rate approximately doubled for exposed tin oxide areas between 80% and 10% of the substrate area. This loading sensitivity was found to increase with increasing power and decreasing Cl2 concentration. It was also observed that local changes in pattern dimensions affected the uniformity of the etch rate. A large photoresist etch rate was observed between one and three times that of the tin oxide and it decreased as the area of photoresist coverage increased. Linewidth loss, up to 4 μm at high powers, was overcome using improved ultraviolet exposure, leading to feature resolution capabilities of <5 μm. Etch rate inhomogeneity was also observed on a local scale, possibly due to redeposition of sputtered photoresist. Overetching, however, ensures rapid clearing of tin oxide islands without damage to the underlying SiO2 buffer layer.

A mechanism of gate oxide deterioration during As/sup +/ ion implantation

The deterioration or catastrophic breakdown of thin gate oxides during ion implantation is studied. The effect of ion beam density, the distribution of the gate oxide deterioration over a wafer, and the effect of photoresist coverage are shown quantitatively by measuring the number of interface states generated in MOS capacitors. It is shown that the four charge sources contribute to the deterioration of gate oxide: the irradiated ion beam, the secondary electrons emitted from the gate electrode, the charges accumulated on the photoresist surface around the gate electrode, and the secondary electrons emitted from a wafer holder. The first three charges accelerate the deterioration of the gate oxide and the last one reduces it. A model of the gate oxide deterioration in ion implantation that is very useful for finding methods of reducing the charging damage is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of Photoresist on Plasma Etching

Etching characteristics of polysilicon and silicon dioxide with various photoresist coverages have been investigated to reveal the role played by the photoresist in chlorinated plasma. The etch rate of oxide decreases with decreasing coverage of photoresist on the wafer. Although the nominal etch rate of polysilicon is not sensitive to the photoresist coverage, the etch rate of polysilicon patterned with oxide mask is higher than that with photoresist mask. Chlorocarbon species originated from the photoresist erosion are speculated to be responsible for these behaviors. Furthermore, we have observed that there is a strong loading effect in polysilicon etching with chlorinated plasma if a nonerodible mask is used, but this effect is suppressed by the presence of a photoresist.

Patterning of Submicron Metal Features and Pillars in Multilevel Metallization

A novel multilevel interconnect scheme has been developed as part of an advanced submicron CMOS process technology. A salient feature of this interconnect scheme is the use of metal pillars for vertical connections between the devices on the substrate and the first level of metallization, as well as between successive levels of metallization, in place of the conventional etched contacts and vias. The pillar and conductor levels, with feature dimensions below 1 μm, were defined using contrast enhancement lithography and reactive ion etching. The application of these techniques to the definition of small and sparse photoresist features on an uneven metallic substrate and to the subsequent pattern transfer to the underlying metal films is described. The issues of surface topography and reflectivity, small‐area photoresist coverage, and dimension and profile control in the patterning of submicron features are addressed.