Patterning of Submicron Metal Features and Pillars in Multilevel Metallization

Abstract

A novel multilevel interconnect scheme has been developed as part of an advanced submicron CMOS process technology. A salient feature of this interconnect scheme is the use of metal pillars for vertical connections between the devices on the substrate and the first level of metallization, as well as between successive levels of metallization, in place of the conventional etched contacts and vias. The pillar and conductor levels, with feature dimensions below 1 μm, were defined using contrast enhancement lithography and reactive ion etching. The application of these techniques to the definition of small and sparse photoresist features on an uneven metallic substrate and to the subsequent pattern transfer to the underlying metal films is described. The issues of surface topography and reflectivity, small‐area photoresist coverage, and dimension and profile control in the patterning of submicron features are addressed.