Photonic Research Articles

Wafer and chip-level characterization of edge-coupled photonic integrated circuits by cascaded grating couplers and spot-size converters

This study presents an efficient testing process for characterizing silicon photonic ICs. This process utilizes a coupling structure that integrates grating couplers and spot-size converters for efficient testing both at the chip and wafer levels, respectively. By leveraging wafer-level testing to estimate the characteristics of final chip-level devices, we anticipate a reduction in testing costs. To demonstrate the validity of the proposed testing process, we fabricated and measured silicon-on-insulator ring resonator devices on both wafer and chip levels. The results showed good agreement between the two levels of measurement, validating the effectiveness of our proposed testing process.

Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC

Abstract The trends in co-packaged optics will be investigated in this study. Emphasis is placed on the heterogeneous integration of photonic IC (PIC) and electronic IC (EIC). In particular, 2D and 3D heterogeneous integration of ASIC Switch, PIC and EIC w/o bridges, and heterogeneous integration of ASIC Switch, PIC and EIC on glass substrate will be discussed. Some recommendations will be provided.

1 × 4 nano-pixel power splitter designed using an electric profile correlation coefficient monitor method

The power splitter is one of the fundamental elements in a photonic IC. Among various power splitter structures, nano-pixel-based ones have attracted attention in recent years because of their flexible design capability. As there is no rigid design rule in nano-pixel layout, typically, inverse design algorithms are employed to realize the target function. In inverse design, general criteria are needed during the design process, and one typical criterion is the excess loss, however, there are no specific criteria for mode field evaluation. When designing a 1 × N power splitter, considering the power balance among the N output ports is crucial, therefore, we propose a correlation coefficient method to evaluate the output electric field profile. In this study, we adopted vector criteria including both an excess loss and correlation coefficient method during the inverse design process. As a result, the simulated results show all four 0th order modes and the output power to be 24.490%, 24.494%, 24.494%, and 24.490% with a low excess loss of 0.1 dB.

WLCSP Fully Protected Fan-In Reliability

A strong supply chain requires higher performance and lower cost processes. DCA conventionally referred to as WLCSP has been used for low density devices, however for higher density devices reliability concerns have emerged. Six-side protected, aka “6S or fully protected”, CSP is a rapidly growing market. Fully protected CSP was first implemented with processes such as M-series utilizing FO. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations. These steps can be eliminated in a P-WLCSP process to provide the cost-effective high reliability 6S format needed for high-performance higher pin count and/or thin silicon chips. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking and thin board applications. The P-WLCSP process incorporates the best of DCA (simplicity) and FO (protection) while incorporating advanced manufacturing processes to lower cost and improve performance. This paper builds on the SoP-TM process release announced at the 2023 Device Packaging Conference earlier this year with the addition of reliability characterization beyond first silicon data for electrical test chips. Reliability data such as accelerated stress tests, die strength, operating lifetime and thermal testing are key areas of investigation for the new P-WLCSP technology that will be presented. The presentation will also include and update for ultra-thin device reliability test methods under consideration for new NIST standards.

Rate equation analysis for deterministic and unidirectional lasing in ring resonators with an S-shaped coupler

Ring resonators are traditionally popular optical devices that apply to various components in photonic ICs. They also play an important role in the on-chip generation of many novel optical states in topological systems and non-Hermitian systems. Unidirectional lasing of ring resonators is used in many such systems to create exotic states of light including optical vortexes and optical skyrmions, but the unidirectional behavior has not been fully understood. Previous research has constructed a simplified model to explain the steady state behaviors of unidirectional ring resonators, but the carrier dynamics and spontaneous emission were omitted. In this work, we give a numerical analysis of unidirectional ring resonators with an S-shaped coupler. We identified the importance of the gain saturation to robustness against backscattering and high unidirectionality by comparing to the model without saturation. We also discuss the effect of asymmetrical coupling on the deterministic realization of unidirectionality.

Thin and Ultra-thin Sidewall Protected P-WLCSP

Diversity in packaging for a strong supply chain requires higher performance and lower cost processes for new manufacturers. Six-side protected, aka “6S or fully protected”, CSP is an emerging and rapidly growing market. Fully protected CSP (without substrates or lead-frames) was first implemented with processes such as M-series and eWLB. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations most common to FO to obtain 6-side die protection. These steps can be eliminated in a wafer level process to provide high-performance low-cost P-WLCSP to enable new CSP manufacturing capability, Fan-In and Chiplets. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking, and thin board applications. This paper builds on the SoP-TM process development provided at the IMAPS Symposium earlier this year with the addition of first silicon data for electrical test chips. SoP-TM test chip features include 10um silicon thickness, metal interconnect and micro-bumps, smooth silicon sidewalls and 6-side polyimide encasement. Reliability data and testing is a key area of investigation for thin-device technology. Ultra-thin device reliability test methods under consideration for new NIST standards will be presented. Mechanical, high temperature and high humidity reliability for SoP-TM test chips, Chip-on-Flex (COF) and Flip Chip using the new test methods will be presented.

Valley photonic crystal waveguides fabricated with CMOS-compatible process

Valley photonic crystal (VPhC) waveguides have attracted much attention because of their ability to enable robust light propagation against sharp bends. However, their demonstration using a CMOS-compatible process suitable for mass production has not yet been reported at the telecom wavelengths. Here, by tailoring the photomask to suppress the optical proximity effect, VPhC patterns comprising equilateral triangular holes were successfully fabricated using photolithography. We optically characterized the fabricated VPhC devices using microscopic optics with NIR imaging. For comparison, we also fabricated and characterized line-defect W1 PhC waveguides, in which the transmission intensities decreased at some regions within the operating bandwidth when sharp turns were introduced into the waveguide. In contrast, the developed VPhC waveguides can robustly propagate light around the C-band telecommunication wavelengths, even in the presence of sharp bends. Our results highlight the potential of VPhC waveguides as an interconnection technology in silicon topological photonic ICs.

Low-loss silicon nitride photonic ICs for near-infrared wavelength bandwidth.

Low-loss photonic integrated circuits (PICs) are the key elements in future quantum technologies, nonlinear photonics and neural networks. The low-loss photonic circuits technology targeting C-band application is well established across multi-project wafer (MPW) fabs, whereas near-infrared (NIR) PICs suitable for the state-of-the-art single-photon sources are still underdeveloped. Here, we report the labs-scale process optimization and optical characterization of low-loss tunable photonic integrated circuits for single-photon applications. We demonstrate the lowest propagation losses to the date (as low as 0.55 dB/cm at 925 nm wavelength) in single-mode silicon nitride submicron waveguides (220×550 nm). This performance is achieved due to advanced e-beam lithography and inductively coupled plasma reactive ion etching steps which yields waveguides vertical sidewalls with down to 0.85 nm sidewall roughness. These results provide a chip-scale low-loss PIC platform that could be even further improved with high quality SiO2 cladding, chemical-mechanical polishing and multistep annealing for extra-strict single-photon applications.

PoBO: A Polynomial Bounding Method for Chance-Constrained Yield-Aware Optimization of Photonic ICs

Conventional yield optimization algorithms try to maximize the success rate of a circuit under process variations. These methods often obtain a high yield but reach a design performance that is far from the optimal value. This article investigates an alternative yield-aware optimization for photonic ICs: we will optimize the circuit design performance while ensuring a high yield requirement. This problem was recently formulated as a chance-constrained optimization, and the chance constraint was converted to a stronger constraint with statistical moments. Such a conversion reduces the feasible set and sometimes leads to an over-conservative design. To address this fundamental challenge, this article proposes a carefully designed polynomial function, called optimal polynomial kinship function, to bound the chance constraint more accurately. We modify existing kinship functions via relaxing the independence and convexity requirements, which fits our more general uncertainty modeling and tightens the bounding functions. The proposed method enables a global optimum search for the design variables via polynomial optimization. We validate this method with a synthetic function and two photonic IC design benchmarks, showing that our method can obtain better design performance while meeting a prespecified yield requirement. Many other advanced problems of yield-aware optimization and more general safety-critical design/control can be solved based on this work in the future.

High-efficiency SOI-based metalenses at telecommunication wavelengths

Abstract We demonstrated silicon-on-insulator (SOI)-based high-efficiency metalenses at telecommunication wavelengths that are integrable with a standard 220 nm-thick silicon photonic chip. A negative electron-beam resist (ma-N) was placed on top of the Si nanodisk, providing vertical symmetry to realize high efficiency. A metasurface with a Si/ma-N disk array was numerically investigated to design a metalens that showed that a Si/ma-N metalens could focus the incident beam six times stronger than a Si metalens without ma-N. Metalenses with a thick ma-N layer have been experimentally demonstrated to focus the beam strongly at the focal point and have a long depth of field at telecommunication wavelengths. A short focal length of 10 μm with a wavelength-scale spot diameter of approximately 2.5 μm was realized at 1530 nm. This miniaturized high-efficiency metalens with a short focal length can provide a platform for ultrasensitive sensors on silicon photonic IC.

About the cover: Advanced Photonics Volume 2, Issue 6

About the cover: Advanced Photonics Volume 2, Issue 6

About the cover: Advanced Photonics Volume 3, Issue 3

About the cover: Advanced Photonics Volume 3, Issue 3

Foundry-processed optomechanical photonic integrated circuits: publisher’s note

This publisher’s note amends the author list of [OSA Continuum 4, 1215 (2021)10.1364/OSAC.419410].

About the cover: Advanced Photonics Volume 3, Issue 2

About the cover: Advanced Photonics Volume 3, Issue 2

Photonics: 20/20 Vision

Photonics: 20/20 Vision

Nonlinear INtegrated Photonics

Nonlinear INtegrated Photonics

Design of a photonic crystal fiber with low confinement loss and high birefringence

A photonic crystal fiber (PCF) for long distance communication was proposed in this paper. The circular and elliptical air holes distribute in the cladding, and there are two small elliptical air holes around the core in cross section of the PCF. The characteristics of the PCF were analyzed by using the finite element method (FEM) sys-tematically. The results show that the PCF offers an ultrahigh birefringence of 3.51×10-2 and the confinement loss as low as 1.5×10-9 dB/m with the optimal structure at the wavelength of 1550 nm. Compared with the existing photonic crystal fibers with elliptical air holes, the birefringence has a large increase, and the confinement loss reduces by 5 orders of magnitude. Additionally, we also analyzed the relationship between the dispersion of the PCF and the wavelength, and obtained the Brillouin gain spectrum characteristics. In general, the PCF can be used in long distance communication system.

A Study on the Analysis of Electromagnetic Characteristics and Design of a Cylindrical Photonic Crystal Waveguide with a Low-Index Core

A Study on the Analysis of Electromagnetic Characteristics and Design of a Cylindrical Photonic Crystal Waveguide with a Low-Index Core

About the cover: Advanced Photonics Volume 3, Issue 1

About the cover: Advanced Photonics Volume 3, Issue 1

Twenty Years of Photonics

Twenty Years of Photonics