Photoelectric Laser Stimulation Research Articles

Circuit simulation assisting Physical Fault Isolation for effective root cause analysis

In this study, the PFI (Physical Fault Isolation) was assisted with the analog circuit simulation to provide insight into the device performance under the failed condition and the failure mechanisms. This approach allows us to choose and apply the right PFI technique to find the failure root cause in a very time effective manner and propose the failure mode hypothesis. Accordingly, as an alternative to the conventional circuit modification approaches a backside PLS (Photoelectric Laser Stimulation) based technique was applied to the suspicious analog block. In this technique, a laser with the wavelength in the NIR (Near Infrared) range stimulates the analog circuit block at the transistor level and changes the device electrical state from fail to pass. Consequently, we could evaluate the circuit behaviour at failed condition and verify the failure. In this manner, the competent combination of PFI and analog circuit simulation successfully leads us to the corrective action to improve the circuit design and overcome the inevitable fabrication process variation.

Electrical model of an inverter body-biased structure in triple-well technology under pulsed photoelectric laser stimulation

This study is driven by the need to optimize reliability and failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. Nowadays, single event effect (SEE) evaluations due to radiation impacts are critical in fault tolerance and security field. The prediction of a SEE occurring on electronic devices is proposed by the determination and modeling of the phenomena under pulsed laser stimulation. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an inverter in a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals the possible activation change of the parasitic bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation. Therefore this electrical model could be used as a tool for characterizing more complex CMOS circuits under photoelectrical laser stimulation.

Effects of 1064 nm laser on MOS capacitor

This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064nm) on a 90nm technology metal–oxide–semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps.

Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90 nm technology

This paper presents the electrical model of a PMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures. It permits to simulate the effect of a continuous wave laser on a PMOS transistor by taking into account the laser’s parameters (i.e. spot size and location, or power) and the PMOS’ geometry and bias. It offers a significant gain of time by comparison with experiments and makes possible to build 3D photocurrent cartographies generated by the laser on the PMOS.

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

This paper describes a new technique that uses a 1064nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains.

Laser induced impact ionization effect in MOSFET during 1064 nm laser stimulation

Laser stimulation with 1300nm as thermal (TLS) and with 1064nm as photoelectric (PLS) laser stimulation techniques are now widely used in failure analysis of Integrated Circuits. The stimulation signatures when using a 1064nm laser are often a combination of PLS and TLS along with laser induced impact ionization. The results show the existence of laser induce impact ionization current component when high laser power is applied. This work presents a quantitative investigation of 1064nm laser stimulation effects on single NMOSFET devices. For high laser power applications the impact ionization current becomes the dominant component for 1064nm laser stimulation.

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal-oxide-semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.

Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs

The mixed-mode ICs (Integrated Circuits), by involving multiple functions (digital, analog, RF, power) inside one device, are becoming more compact and useful. At the same time, their developments and Failure Analysis (FA) are more and more complex: test, diagnostic and defect localization steps are harder and longer in time. Each step needs to be improved as far as defect localization is concerned. Several techniques based on emission microscopy, electron beam, direct probing or laser stimulation have been developed and introduced to follow these ICs evolutions. The most recent evolution in the laser stimulation field has been the introduction of several dynamic laser stimulation techniques aimed to localize defects or weakness regions inside functional but failing ICs (environmental marginalities related to temperature, frequency, voltage, etc.). This paper deals with the use of dynamic photoelectric laser stimulation techniques applied on mixed-mode ICs where the major difficulty is due to their considerable intrinsic sensitivity. Indeed, the analog circuitry is more sensitive than the digital circuitry since a slight change in an electrical parameter can trigger a functionality failure. This property limits the defect localization because of the complex interpretation of the results, the laser stimulation mapping. We propose to help the failure analyst by coupling the dynamic laser stimulation mapping with the photoelectric impact simulations run on a previously analyzed structure. The goal is to predict and interpret the laser sensitivity mapping so to isolate the defective areas in the analog devices.

Time resolved imaging using synchronous picosecond Photoelectric Laser Stimulation

This paper presents an improvement of the time resolution of the Photoelectric Laser Stimulation technique using the phase of a mode-locked laser as a reference to generate an electrical stimulus for the device under test. This synchronization system was applied to observe signal propagation in an 860 MHz ring oscillator.

From Static Thermal and Photoelectric Laser Stimulation (TLS/PLS) to Dynamic Laser Testing

From Static Thermal and Photoelectric Laser Stimulation (TLS/PLS) to Dynamic Laser Testing

Silicon wafer reclamation—a processing service : John E. Lawrence. Electron. Prod. p. 43 (September 1976)

This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064 nm) on a 90 nm technology metal–oxide–semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps.