Phosphorus-doped Polysilicon Emitter Research Articles

Impact of ex-situ and in-situ cleans on the performance of bipolar transistors with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts

This paper investigates the effects of an in-situ hydrogen bake and an ex-situ hydrofluoric acid (HF) etch prior to polysilicon deposition on the electrical characteristics of bipolar transistors fabricated with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts. Emitter contact deposition in a UHV-compatible low pressure chemical vapor deposition (LPCVD) cluster tool is also compared with deposition in a LPCVD furnace. Transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS) are used to characterize the emitter contact material and the interface structure and a comparison is made with Gummel plots and emitter resistances on bipolar transistors. The SIMS results show that an in-situ hydrogen bake in a cluster tool gives an extremely low oxygen dose at the interface of 6.3/spl times/10/sup 13/ cm/sup -2/, compared with 7.7/spl times/ 10/sup 14/ and 2.9/spl times/10/sup 15/ cm/sup -2/ for an ex-situ HF etch and deposition in a cluster tool or a LPCVD furnace, respectively. TEM shows that the in-situ hydrogen bake results in single-crystal silicon with a high density of defects, including dislocations and twins. The ex-situ HF etch gives polycrystalline silicon for deposition in both a cluster tool and a LPCVD furnace. The single-crystal silicon emitter contact has an extremely low emitter resistance of 21 /spl Omega/./spl mu/m/sup 2/ in spite of the high defect density and the light emitter anneal of 30 s at 900/spl deg/C. This compares with emitter resistances of 151 and 260 /spl Omega/./spl mu/ m/sup 2/ for the polycrystalline silicon contacts produced using an ex-situ HF etch and deposition in a cluster tool or a LPCVD furnace, respectively. These values of emitter resistance correlate well with the interface oxygen doses and the structure of the interfacial oxide layer. The high defect density in the single-crystal silicon is considered to be due to the high concentration of phosphorus (>5/spl times/10/sup 19/ cm/sup -3/) in the as-deposited layers.

Analysis of emitter efficiency enhancement induced by residual stress for in situ phosphorus-doped polysilicon emitter transistors

This paper analyzes the enhancement of emitter efficiency in in situ phosphorus-doped polysilicon (IDP) emitter transistors, whose polysilicon emitter is crystallized from an in situ phosphorus-doped amorphous Si film. There are two factors that enhance the emitter efficiency of the IDP emitter. One is a potential barrier at the LDP/substrate interface produced by residual stress in the IDP layer. The other is a very thin oxide layer at the interface, which prevents epitaxial growth at the interface. We have distinguished between the emitter efficiency enhancement due to each of these two factors by analyzing the characteristics of three types of IDP emitter in which the residual stress and the thin oxide layer at the interface are controlled differently. We found that the potential barrier due to the residual stress increases the emitter efficiency from about two times to about eight times depending on the emitter size, and that the thin oxide layer at the interface increases the emitter efficiency by about three times.

In situ phosphorus-doped polysilicon emitter technology for very high-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-/spl mu/m emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed.

Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

The effect of rapid solid-phase epitaxy (SPE) on the current gain of in situ phosphorus-doped polysilicon-emitter (IDP) transistors has been evaluated, IDP technology is used to produce very-high-speed small-emitter bipolar transistors, which have very high current gain due to their hetero-emitter-like characteristics. The IDP film is deposited on a clean poly/mono-silicon surface, followed by rapid thermal annealing (RTA). The poly/mono interface was analyzed and the lattice image was observed by high-resolution transmission electron microscopy (TEM). The majority of the IDP transistors had poly/mono-silicon interfacial hetero-emitter-like characteristics and thus had high current gain. The remaining transistors, however, did not exhibit hetero-emitter-like characteristics due to SPE and thus the current gain was reduced. These results are well explained using an interfacial residual-stress model: rapid epitaxy occurs when the amorphous silicon film is annealed by RTA, which eliminates the interfacial residual stress and in turn the hetero-emitter-like characteristics.

113-GHz f/sub T/ graded-base SiGe HBT's

Summary form only given. A novel low-thermal cycle process was used to fabricate epitaxial SiGe-base heterojunction bipolar transistors (HBTs) with record unity current gain cutoff frequencies. The process includes an in situ phosphorus-doped polysilicon emitter which requires only a 800 degrees C-10-s anneal. A peak f/sub T/ of 113 GHz at V/sub CB/ of 1 V was obtained for an intrinsic base sheet resistance of 7 k Omega / Square Operator . >

Rapid thermal annealing of in situ phosphorus-doped polysilicon emitters

Rapid thermal annealing of in situ phosphorus-doped polysilicon emitter transistors in the temperature range 850–1000 °C greatly reduces the emitter resistance RE at the cost of a slight increase in hole back injection, seen as a decrease in emitter Gummel number GE. Annealing at 1000 °C for 5 s gives low emitter resistance (RE ≈ 100 Ω μm2) while maintaining good suppression of back injection (GE ≥ 1014 scm−4). Annealing at temperatures below 1000 °C fails to reduce RE sufficiently for use in high-speed devices.

Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

This paper presents a detailed comparison of the measured and computed electrical characteristics of polysilicon emitter bi-polar transistors over a wide range of processing conditions. Detailed electrical measurements are made of both the emitter resistance and the base and collector current as a function of base-emitter voltage. Devices with arsenic- and phosphorus-doped emitters are considered, as well as both with and without a deliberately grown interfacial oxide layer. The theoretical characteristics are computed using a unified model that incorporates both transport and tunneling mechanisms. It is shown that the measured emitter resistances across a wide range of processing conditions can be satisfactorily explained using a tunneling model with a single value for the electron effective barrier height (0.4 eV). Values for the modeling parameters are obtained, in some cases uniquely by measurement, and in others by fitting the experimental results. In devices with a deliberately grown interfacial oxide, the base current is suppressed to such an extent that recombination in the single-crystal emitter and in the base becomes important.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.