Phase-locked Loop Circuit Research Articles

Application and practice of portable bi-directional DC-AC energy storage converter based on second order generalized integrator phase-locked loop and HERIC circuit

In various industries, including the production of new energy and electric vehicles, portable bidirectional converters are crucial for enhancing power supply reliability. In recent years, these converters have become increasingly normal in daily life. Bidirectional converters have not been as popular or have not been used as much due to issues with phase tracking on grids connected to leakage current in the converter system. The essential features and principles of the portable bidirectional energy storage converter proposed in this paper, which is based on a second-order generalized integrator phase-locked loop, are theoretically investigated. Formulas are also generated using small signals to address this issue. PLECS simulation software was used for parameter design and algorithm simulation to test the effectiveness of the phase-locked loop under various operating situations. Therefore, a set of appropriate phase-locked structure models for this circuit was developed. An experimental verification platform was constructed to confirm the accuracy of the design parameters: the front stage uses the H-bridge; the backstage, which uses the front stage, adopts the H-bridge; and the rear stage adopts the topology platform of the HERIC topology + LCL filter circuit. The test data indicates that, the addition of the HERIC topology and soft switching resulted in a 94 % reduction in leakage current and a 1.6 % improvement in efficiency. Analysis and comparison results of the test data confirmed the consistency between the experimental effect and the design parameters, achieving the expected effect and proving the accuracy of the topology and mathematical model. The design methodology and design parameters of this thesis are useful and instructive for similar or related research.

Frequency source design of solid-state microwave source based on phase-locked loop technology

Abstract A high-performance frequency synthesizer based on phase-locked loop (PLL) technology is proposed for high-power, solid-state microwave sources. The PLL circuit is simulated, optimized, and analyzed by using ADIsimPLL software. The methods to improve the phase noise performance of the frequency source are summarized. Using ADF4351, STM32, ADL5611, and other devices to complete the hardware circuit and software control part of the design, the low noise frequency source is successfully established. The frequency source can output the signal in the frequency range of 2.3 G-2.5 G, the phase noise is within - 97.30 dBc@1 KHz, the output power reaches 20 dBm, the overall performance is excellent, and meets the requirements of a solid-state microwave source.

Design of an Electromagnetic Micro Mirror Driving System for LiDAR.

Electromagnetic micro mirrors are in great demand for light detection and ranging (LiDAR) applications due to their light weight and low power consumption. The driven frequency of electromagnetic micro mirrors is very important to their performance and consumption. An electromagnetic micro mirror system is proposed in this paper. The model of the system was composed of a micro mirror, an integrated piezoresistive (PR) sensor, and a driving circuit was developed. The twisting angle of the mirror edge was monitored by an integrated PR sensor, which provides frequency feedback signals, and the PR sensor has good sensitivity and linearity in testing, with a maximum of 24.45 mV/deg. Stable sinusoidal voltage excitation and frequency tracking was realized via a phase-locked loop (PLL) in the driving circuit, with a frequency error within 10 Hz. Compared with other high-cost solutions using PLL circuits, it has greater advantages in power consumption, cost, and occupied area. The mechanical and piezoresistive properties of micro mirrors were performed in ANSYS 19.2 software. The behavior-level models of devices, circuits, and systems were validated by MATLAB R2023a Simulink, which contributes to the research on the large-angle deflection and low-power-consumption drive of the electromagnetic micro mirror. The maximum optical scan angle reached 37.6° at 4 kHz in the behavior-level model of the micro mirror.

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

Design of liquid level detection circuit based on sampling probe structure capacitance.

Liquid level detection system is an essential core functional component of automatic clinical medical testing instrument. The conventional liquid level detection method has low detection accuracy and sensitivity, and may have the problem of false detection, which may lead to the inaccurate test results. This paper presents a high sensitivity liquid level detection system based on the principle of variable capacitance. When the sampling probe contacts the liquid level, the probe capacitance will change. The liquid level detection circuit board judges whether the probe contacts the liquid level by sensing the change of probe capacitance. When judging the liquid level signal, the combination of slope detection and amplitude detection is used. The liquid level detection circuit board takes the phase-locked loop(PLL) circuit as the center to detect the change of the capacitance. The reference signal of the PLL is set as a square wave of 375kHz. The double tube probe is used as a part of the tuning capacitor of the voltage controlled oscillator to control the frequency of the output signal, which can realize the rapid phase locking. The experimental results show that the system has accurate detection results, high sensitivity, stable and reliable operation, good dynamic response performance in the case of large and small liquid volume. Compared with other liquid level detection methods based on machine vision, ultrasonic, optics and so on, the proposed liquid level detection system has simpler structure and lower cost, it can avoid the problems of collision, carryover contamination and empty suction by controlling the depth of sampling needle inserted into liquid.

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.

Fractional delay Newton structure for Lagrangian interpolation in PV integrated grid connected system

SummaryThis paper proposes a fractional delay (FD) Newton structure for Lagrangian interpolation in single phase grid integrated photovoltaic (PV) system. The structure has been designed for achieving shunt compensation and as a phase locked loop circuit for synchronization. The designed controller performs multiple tasks of feeding the active power to meet the load demand and simultaneously providing reactive power compensation, power factor improvement, and compensating other power quality voltage and load current harmonics. Further, synchronization poses a severe challenge in integrating the PV power electronic converters to the grid. The FD filter is used to discretize the continuous time signal at any time instant using interpolation algorithm employing the non‐integral value of the sampling rate delays. The FD delay filter is made adaptive and self‐learning by using least mean square algorithm. The designed synchronization technique meets the objective of faithfully tracking the phase of the grid voltage under all grid disturbances such as under voltage, overvoltage, frequency variations, and phase angle disturbances in a precise manner.

Simple, low-cost, and well-performing optical phase-locked loop for frequency and phase locking of semiconductor lasers.

We demonstrate a simple, low-cost, and well-performing optical phase-locked loop (OPLL) circuit with ADF4007 as the phase frequency detector chip to achieve frequency and phase locking of two semiconductor lasers in both short and long terms. The measured short term performances, determined by fast feedback, show that the spectral width of the beat signal is low, around 1Hz, and the residual phasing error is 0.04r a d 2. The measured long term performances, determined by slow feedback, show that the drift of the central frequency of the beat signal is within 1.1(1)Hz in 2h, and the derived Allan deviation is less than 0.4Hz within all integration times of up to 1000s. The phase noise measurement shows a suppression of phase noise of the beat signal from free running to closed-loop OPLLs in a Fourier frequency of 10Hz-20kHz. These measurements show that the OPLL circuit we modified can fit most scientific experiments requiring a fixed frequency difference and phase coherence.

Rotor Field-Oriented Control of Doubly Fed Induction Generator in Wind Energy Conversion System

In this study, robust and high-performance vector control of a rotor side converter (RSC) was performed for stability and efficient operation doubly fed induction generator (DFIG) based on the variable speed wind turbine (VSWT). The mathematical model of the DFIG is simulated in the computer. Amplitude and frequency of the voltage in the DFIG were controlled for different values of load and variable speeds. In the experimental study, a DFIG-based wind turbine system was set up in the laboratory. The field position of the stator was detected from stator voltages by a phase-locked loop (PLL) circuit. The rotor position was measured with an incremental encoder connected to the rotor shaft of the DFIG. The angular position of the slip was calculated by the difference between the rotor and the stator field positions. The frequency and amplitude of rotor currents were determined with the angular position of slip. To generate output voltages of converter feeding rotor windings, the space vector pulse width modulation (SVPWM) technique was used. In the experimental study, the RSC was controlled with the DS1103 board. The prepared experiment set was tested at different operating speeds.

A Resonant Electrostatic Field Microsensor With Self-Compensation for Sensitivity Drift

Electrostatic field microsensors (EFMs) are widely used in many fields, and the environmental adaptability is one of the major concerns for EFMs development. This paper proposes a resonant EFM with self-compensation for sensitivity drift, which is suitable for outdoor applications. The proposed EFM sensitive structure mainly consists of sensing electrodes and reference electrodes, where the sensing electrodes are designed to measure the electrostatic field, and the reference electrodes are used to detect the vibration amplitude and phase of the movable structure. With the reference electrodes output, the EFM can track the resonant frequency by phase-locked loop circuit automatically and correct the sensing output signal in real time. Experimental results demonstrated that the proposed EFM reached a linearity of 0.21% and a total uncertainty of three round trips within 1.34% in the electrostatic field range of ±18 kV/m, and achieved a sensitivity drift within 3.0% in the temperature range of -40~70 °C, which means that it realized a good self-compensation performance.

Hybrid Multibeamforming Receiver With High-Precision Beam Steering for Low Earth Orbit Satellite Communication

A hybrid multibeamforming receiver for low Earth orbit (LEO) satellite communication in the Ku-band is designed and tested. The proposed receiver is implemented with eight channels to enable multibeam control. The proposed receiver, including both analog and digital beamforming structures, is capable of multibeam reception using both analog and digital beamforming techniques simultaneously or selectively. Analog beamforming is implemented by employing a local oscillator phase shifter using direct digital synthesis and phase-locked loop (PLL) structures. In digital beamforming, a software-defined radio can control the phase of the signal in the digital baseband. The multibeam received using the proposed hybrid multibeamforming receiver was measured at 11.7 GHz and 12.7 GHz in an anechoic chamber. The phase-control resolutions of analog and digital beamforming were 0.022° and 0.72°, respectively. Analog beam-switching speed is slower than digital beamforming because it depends on the settling time of the PLL circuit, but it has a high phase-control resolution. Therefore, by using analog and digital beamforming when precise beam tilting and fast beam switching are required, respectively, the proposed hybrid multibeamforming is shown to be suitable in accordance with the communication situation.

Design of a high‐performance advanced phase locked loop with high stability external loop filter

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase-frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage-controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase-frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage-controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed-forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide-by-47 and divide-by-48) that lacks a few extra flip-flops which save considerable power and improves the frequency difficulties of the multi-band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1-μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS-based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

Design of Noncoherent and Coherent Receivers for Chirp Spread Spectrum Systems

LoRaWAN is a prominent communication standard to enable reliable low-power, long-range communications for the Internet of Things (IoT). The modulation technique used in LoRaWAN, commonly known as LoRa modulation, is based on the principle of chirp spread spectrum (CSS). The main objective of this article is to design a practical, low-complexity coherent receiver for a recently proposed CSS-based modulation scheme, called phase-shift keying CSS (PSK-CSS), that embeds extra information bits in the starting phases of conventional CSS symbols. To this end, a novel method is proposed to perform coarse timing and frequency synchronization that makes use of a preamble consisting of both up and down chirps and the shape of the pulse shaping and/or receive (matched) filters. Furthermore, to enable fine synchronization, timing, and phase loop filters are designed as simple first-order and second-order phase-locked loop (PLL) circuits with dynamic gain control. A natural outcome of our design is a practical noncoherent receiver that can be used for the conventional LoRa/CSS system and has better performance and/or lower computational complexity as compared to other existing designs. Extensive simulation results are presented to demonstrate the excellent performance and merits of the proposed design. In particular, the bit-error-rate (BER) performance of the higher-rate PSK-CSS system obtained with the proposed coherent receiver is only 0.25 dB worse than that obtained with the ideal co-coherent receiver, whereas it enjoys about 0.75-dB power gain over the noncoherent detection performance of the conventional CSS system. Thanks to the extra information bits carried by the phases of CSS symbols, the PSK-CSS system implemented with quadrature phase-shift keying (QPSK) delivers additional 23.44% and 18.75% data rate as compared to the conventional CSS system for the spreading factors (SFs) of 8 and 10, respectively.

An Implantable Phase Locked Loop MEMS-Based Readout System for Heart Transplantation

An implantable readout circuit using a MEMS pressure sensor has been designed and implemented to monitor the heart activity after heart transplant surgery. It features a time domain architecture using two identical voltage-controlled oscillators and phase locked loop circuits. The circuit was implemented in a 65 nm CMOS technology with 1 V power supply. It consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100~\mu \text{W}$ </tex-math></inline-formula> power and provides a digital output that is proportional to the analog sensor input with a bandwidth of up to 4 kHz. The SNR of the system is 53 dB. Measurements show the operation of the readout chip with the MEMS sensor.

A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed data paths and a pair of low-speed differential clocks for 512 Gbps BW. To reduce the chip area and power consumption, a common minimal phase-locked loop (MINI-PLL) and data adjustment (CDA) circuit to replaces the clock data recovery circuit (CDR) in the traditional receiver. A delay-matching circuit is adopted to combat PVT variation and lane skew. In addition, a high linearity phase interpolator (PI) circuit design is used in the minimum phase-locked loop (MINI-PLL) to adjust the clock phase and improve the clock jitter performance. Using 28 nm CMOS technology, the overall link power consumption is 1.56 pJ/b. Bit error rate (BER) is less than 10−15 under the real S-parameters with a channel loss of 10db@16GHz.

A system-level method for hardening phase-locked loop to single-event effects

To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ∼ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and irradiated with heavy ions with a linear energy transfer between 1.9 and 65.6 MeV•cm2 mg−1. The proposed radiation-hardened PLL shows one order of single-event effects hardness level higher than the conventional PLL.

An Adaptive Hybrid Control of Grid Tied Inverter for the Reduction of Total Harmonic Distortion and Improvement of Robustness against Grid Impedance Variation

Background: Grid-tied inverters play an efficient role in the integration of renewable energy resources with utility grids. Motivation: However, the interconnection between power converters and the grid has been seen to be responsible for various stability issues such as weak grid, and under weak grid conditions the injection of power to the grid becomes a challenging task due to continuously varying grid impedance affecting the stability margins as a result. Additionally, the grid impedance-related issues boost the voltage harmonics which further devalue its performance. These voltage harmonics propagate through the Phase-Locked Loop (PLL) circuit to the control unit of the inverter which in turn amplifies the low order harmonics of the inverter. Method: The aim of this research is to introduce a novel strategy that decreases the effect of grid impedance-variations on the performance and stability of an inverter. Hence, an adaptive hybrid mode control technique consisting of two parts is proposed in this research. The current regulator part is implemented in a synchronous reference frame for its gain and time parameters to improve the performance, stability, and response time. The adaptive harmonic compensators are implemented in a stationary reference frame for harmonic compensation purposes. This adaptive nature of harmonic compensator can effectively work in the case of frequency variation where the fixed value based harmonic compensator fails. Results: The adaptive harmonic compensators improve the performance by reducing total harmonic distortion (THD), reduce computation and improve stability when the grid has distorted voltage, variation in grid impedance and frequency. Impact and utility: Our results show that the system becomes less sensitive to grid impedance variations which makes the proposed technique very relevant to the stability performance applications.

Low-Range Tracking Radio Altimeter with a Phase-Locked Loop

Introduction. The article proposes a new principle for designing a low-range tracking radio altimeter based on a phase-locked loop (PLL) for frequency-modulated continuous-wave radar (FMCW) systems.Aim. To develop a model of a low-range tracking radio altimeter, which uses a PLL to estimate the height, as well as to verify its performance via computer simulation.Materials and methods. To solve the problem, we develop a mathematical model of the tracking radio altimeter with an estimator that uses the principles of PLL to generate a reference signal.Results. Computer simulation of a radio altimeter with the PLL circuit to measure the height above a rough surface proves the altitude estimate to be efficient. When operating over a perfectly flat surface, the altimeter provides an efficient altitude estimate for a signal-to-noise ratio greater than 10 dB. When operating over a rough surface under the selected scenario parameters, and the signal-to-noise ratio of 20 dB, the resulting height estimate provides a bias, with its standard deviation growing with increasing the surface roughness. When the standard deviation of the surface roughness is twice the transmission wavelength, the bias and standard deviation of the estimate equal 1 m and 5 m, respectively, under the altimeter height of 150 m. The conducted simulation revealed that the quality of the altimeter performance is subject to abnormal errors, which are caused by deep fading of the received signal due to the signal reflecting from a rough surface.Conclusion. The altimeter under study can be used for estimating the altitude of aircraft flights. Further research will investigate the effect of various factors on the performance quality of the radio altimeter, its circuit implementation and full-scale tests.

Coupling Independent Operation in Wireless Power Transfer System without Ferrite Usage

The power transfer efficiency and output power of a wireless power transfer (WPT) system are mainly affected by magnetic coupling between the primary and secondary coils. This paper presents a constant-current series-series compensated WPT system. Based on the bifurcation criteria, kcri and Lcri, the splitting zero phase angle (ZPA) frequencies is adopted as the operating frequency. The proposed system remains fully compensated even under coupling variations, and without ferrite. The current and voltage gains at the operating frequency can be estimated through the primary current and voltage. A phase-locked loop circuit is used to track the corresponding ZPA frequency due to the coil positioning variations. Experimental results have shown that the 1-kW of output power with the satisfied efficiency of 96%.