Phase-shifted PWM Research Articles

Soft‐switched full‐bridge light‐emitting diode driver with reduced rectifier components

SummaryIn this paper, a new light‐emitting diode (LED) driver based on full‐bridge series resonant converter (SRC) is presented. In the proposed converter LED, load is placed in between DC source and the input side of the full‐bridge inverter which reduces the rectifier components of the SRC. The proposed converter reduces the number of diodes used for rectification and ensures zero voltage switching of the power switches which improves the efficiency of the converter. LED lamp current is regulated with phase‐shift pulse width modulation (PWM) of full‐bridge. Lamp illumination is controlled with PWM dimming. The operation and mathematical analysis of LED driver is presented. To validate the proposed concept, a 40‐W laboratory prototype is developed. Experimental results are presented. Peak efficiency of 93% is obtained.

Bilinear Quadratic Feedback Control of Modular Multilevel Converters

The present paper introduces the formulation and development of a bilinear quadratic control algorithm for Modular Multilevel Converter (MMCs), with a specific emphasis on achieving internal energy stabilization and balance within the converter. A bilinear average model of the MMC is employed, enabling the separation between the DC voltage and the voltage generated by submodules. The algorithm proposed in this study is formulated using bilinear theory and is founded on quadratic feedback control principles. The stability of the suggested controller is scrutinized using a meticulous mathematical approach based on Lyapunov theory. Subsequently, the theoretical findings are assessed using a comprehensive MMC switching model implemented in Matlab Simscape Electrical. The utilization of a phase-shift PWM technique, accompanied by a sorting algorithm, is considered in the study. Additionally, a comparison between the proposed bilinear controller and a standard PI controller is conducted. The outcomes demonstrate that the proposed controller effectively facilitates the regulation of circulating and AC currents, along with managing the internal energy of MMCs. Consequently, this achievement makes a noteworthy contribution to the field, as it introduces an innovative bilinear control approach capable of stabilizing all the state variables of MMCs converters using a single control law.

Average Model-Based Sliding Mode Control for Quality Improvement of a Grid-Connected PUC Inverter

This paper presents a new Sliding Mode Phase-Shift PWM (SM-PSPWM) based control strategy for a grid-connected Packed U-Cell (PUC) inverter. The proposed control strategy is based on the average model of the PUC inverter while using a multi-carriers phase-shift pulse width modulation (PS-PWM) technique. The use of the PWM strategy, based on the inverter average model, ensures high steady-state performance, low harmonic current, and enhanced thermal properties. In addition, the Sliding Mode Control (SMC) is applied to generate the input signals to achieve a fast dynamical response and high robustness against disturbances. To further improve the robustness under parameter mismatch and distorted grid voltage conditions, an integral term is added to the surface function for better accuracy and stability. To validate the performance of the proposed controller (fast dynamics, global stability, low current THD, ...) shown by the simulation results, a laboratory setup is used to validate the theoretical analysis.

VSG Control for Cascaded Three-Phase Bridge Based Battery Inverter

With the increasing number of new energy sources connected to the grid, the unbalanced output of three-phase grid-connected inverters and the lack of no inertia and damping characteristics in the traditional microgrid control system will seriously affect the stability of voltage, frequency, and power angle for microgrids. This paper proposes a novel cascaded three-phase bridge inverter topology for the battery system used for the electric vehicle. Compared with traditional cascaded H-bridge inverters, the proposed multilevel inverter can achieve self-adaptive balance for three phases. The mathematical model of a cascaded three-phase bridge inverter is established in this paper. Based on the voltage and current equations of a multilevel inverter, a new modulation strategy named carrier phase-shifted-distributed pulse width modulation (CPSD-PWM) was developed, which is more suitable for cascaded three-phase bridge inverters. The harmonic analytic equations of carrier phase-shifted pulse width modulation (CPS-PWM) and CPSD-PWM are constructed by the double Fourier analysis method. Compared with the traditional PWM modulation strategy, the CPSD-PWM can reduce the output harmonics and improve the balance of the three-phase output, which can realize the three-phase adaptive balance in the cascaded three-phase bridge inverter. This paper develops a cascaded three-phase bridge multilevel power converter system based on the virtual synchronous generator (VSG) control strategy. The voltage and frequency of inverter output can be accurately controlled in both island mode and grid-connected mode through active power-frequency regulation and reactive power–voltage regulation, and the stability of primary frequency regulation for the multilevel microgrid inverter can be improved by collaborative optimization of virtual inertia and virtual damping. The CPSD-PWM modulation strategy and VSG control strategy are verified by the simulation results and experimental data for the cascaded three-phase bridge inverter.

Self-aligned hybrid carrier-based PWM for modular multilevel converters

The self-aligned hybrid carrier-based pulse-width modulation (PWM) for modular multilevel converters (MMC) based on decentralized control is proposed in this paper. It is based on parallel cells in a submodule (SM) using self-aligned hybrid carrier-based PWM, which combines the concept of level-shifted carrier-based PWM (LSC-PWM) and phase-shifted carrier-based PWM (PSC-PWM) methods. By implementing a decentralized control system digitally, hybrid carriers align themselves. Each SM interacts with the other SMs and each parallel cell in an SM communicates with the other cells to generate hybrid carriers. The proposed control strategy makes advantage of the redundancy idea by adding or removing a cell in the case of cell malfunction and system reconfiguration. A current balancing method is incorporated into the decentralized control system to ensure current balance among parallel cells in an SM. The simulation results illustrate the effectiveness of the presented control method in piecewise linear electrical circuit simulation (PLECS) software.

An Equalization Current Ripple Cancellation (ECRC) Converter-Based Centralized Equalization System for Series-Connected Battery Strings

Battery equalization management is a key technology to ensure the high-performance and safe operation of electrified transportation such as electric vehicles and electric aircraft. In this paper, an equalization current ripple cancellation (ECRC) converter for centralized equalization system is presented. Compared with traditional methods, the ECRC converter-based equalization system achieves a zero-ripple equalization current, so that the unfavorable influence of larger current pulsation on battery cells is eliminated. Meanwhile, under a phase-shifted PWM modulation strategy, the ECRC converter not only implements zero-voltage switching (ZVS) of all switches to reduce switching loss, but also decreases the peak current of the transformer to reduce transformer loss, so that the efficiency of the equalization system is significantly improved. Besides, the value of each power element in the converter is comparatively small, which is conducive to improving the power density of the centralized equalization system. To confirm the theory analysis, an experimental prototype based on a battery string containing 13 cells is built for experimental verification, and a systematic comparison is implemented with existing centralized equalization methods. The experimental and comparison results verify the design of the proposed equalization system and reflect the obvious performance improvement over traditional methods.

Topology and Modulation of Fractional-Level MMC for DC Distribution Grids

For the modular multilevel converter (MMC) with a small quantity of submodules, neither nearest level modulation (NLM) nor carrier phase-shifted pulse width modulation (CPS-PWM) can achieve high voltage quality and low operation loss simultaneously. In this paper, a novel fractional-level MMC (FLMMC) topology is proposed, in which fractional-level submodules are introduced to multiply the output levels. To balance the capacitor voltages between conventional submodules and fractional-level submodules, this paper develops a fractional-level modulation (FLM) method suitable for FLMMC. Considering control complexity and device quantity, the FLMMC with two half-level or one-third-level submodules in each arm is investigated in this paper. Simulation and experiment tests are carried out to validate the effectiveness and superiority of FLMMC under FLM. FLMMC can improve the voltage quality without increasing control complexity, circulating current and switching loss, so as to comprehensively adapt to the power quality requirements of dc distribution grids.

An Improved Topology of Isolated Bidirectional Resonant DC-DC Converter Based on Wide Bandgap Transistors for Electric Vehicle Onboard Chargers

This article proposes an improved topology for an isolated bidirectional resonant DC-DC converter for electric vehicle (EV) onboard chargers. As opposed to the conventional capacitor-inductor-inductor-inductor-capacitor (CLLLC) resonant converter, the proposed converter’s resonant circuit is composed of a capacitor-inductor-inductor-inductor (CLLL) structure, whose inductances, except the capacitor, can be fully integrated with the leakage and mutual inductances of the high-frequency transformer (HF). Therefore, this offers a smaller size, lower costs, minimal power loss, and eventually higher efficiency. Again, the proposed converter design is based on wide bandgap (WBG) transistor switches that operate at MHz-level switching frequency to achieve high power density, high efficiency, and high compactness. A discrete-time proportional integral derivative (PID) controller has been designed using the phase-shifted pulse width modulation (PSPWM) technique to assure closed-loop control of the proposed CLLL converter. The PID controller parameters have been optimized using both the genetic algorithm (GA) and particle swarm optimization (PSO) algorithm and a comparative analysis has been presented between the two algorithms. To achieve fast switching with very little switching loss, the converter is simulated with several wide bandgap (WBG) switching devices. A performance comparison with conventional Si-based switching devices is also provided. A precise power loss model of the semiconductor switches has been devised from the manufacturer’s datasheet to achieve a perfect thermal design for the converter. A 5 kW CLLL converter with an input range of 400–460 V direct current (DC) and an output range of 530–610 V DC, and a switching frequency of 1 MHz has been designed and investigated under various loading scenarios. Gallium nitride (GaN) switching device-based designs achieved the highest levels of efficiency among the switching devices. The efficiency of this device is 97.40 percent in charging mode and 96.67 percent in discharging mode.

Low cost high performance self-starting sensorless single phase induction motor drive

<p><span lang="EN-US">The present paper is directed to achieve a low-cost high-performance self-starting single phase induction motor (SPIM) drive system. A phase shifted pulse width modulation (PWM) trains feeding the motor will replace the starting and running capacitors. Adaptive sliding mode control, enhance with model reference adaptive control (MRAC), is implemented to achieve high performance sensorless SPIM drive. The obtained results confirm the feasibility of the proposed system in starting and fast tracking the reference speed with nearly zero percentage overshoot and zero steady-state error. Moreover, the proposed SPIM drive system is robust to external load torque disturbances and insensitive to system parameter variations. Extensive simulations have been conducted to confirm the validity of the proposed system.</span></p>

An Improved Zero-Voltage and Zero-Current- Switching Phase-Shift Full-Bridge PWM Converter With Low Output Current Ripple

In order to improve the performance of traditional phase-shifted full-bridge converters and reduce the output current ripple, an improved zero voltage and zero current switching phase-shifted full-bridge PWM converter is proposed in this article. By adding a simple auxiliary circuit, the leading-leg switches realize zero voltage switching and the lagging-leg switches realize zero current switching. The primary current is reset during the freewheeling period, so the efficiency of the converter is improved. What is more, the improved converter can effectively reduce the output current ripple. The added auxiliary circuit does not include any lossy components or saturable reactors. The improved phase-shifted full-bridge converter has many advantages, including simple circuit topology, easy implementation of soft switching, high efficiency, and low output current ripple. The operational principle and analysis of the proposed converter are presented in this article. An 800 W experimental prototype is built for experimental verification.

Small-Signal Modeling of Phase-Shifted Digital PWM in Interleaved and Multilevel Converters

In this article, small-signal modeling of digital pulsewidth modulators (DPWMs) used in multicell voltage source converters (VSCs) is addressed. In addition to sampling and computation, DPWM introduces delay, which impairs VSC's dynamic performance and robustness. In order to take into account the influence of modulation delay, an accurate small-signal representation of DPWM is necessary. Here, modeling of multisampled bipolar and unipolar phase-shifted DPWMs for single-, double-, and multi-update strategies is presented. The simplest multilevel modulation of single-cell full-bridge VSCs, unipolar DPWM, is also covered by the analysis. The derived operating-point-dependent small-signal DPWM models are verified using simulated and experimental frequency response measurements up to four times the Nyquist frequency. Comparisons are also made with the models conventionally considered in the literature. Additionally, an approximate method is presented to model the influence of dead time on DPWM's small-signal dynamics. For the purposes of showcasing the importance of the proposed DPWM models, high-frequency admittance of a VSC employing multisampled multiupdate unipolar DPWM is modeled and verified in simulations and experiments.

SOC Balancing Control Method for Cascaded Energy Storage System under Extreme Working Conditions

To solve the problem of an unbalanced state of charge (SOC) between the in-phase sub-modules of the cascaded H-bridge energy storage system, this paper proposed a method based on carrier phase-shifting pulse-width modulation. Different from the traditional in-phase balancing method which is achieved by adding components, by setting the parameter related to the SOC difference to adjust the amplitude of the modulation wave, the new method could solve the problem that the traditional method is not applicable under extreme SOC conditions. The new in-phase SOC balancing method could expand the scenario, and the feasibility of the method is verified by simulation.

A Novel Phase-Shift Pulsewidth Modulation Method for Light-Load Bidirectional Resonant Converter

For the bidirectional full-bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLLC</i> resonant converter, soft switching of primary side and secondary side switches and bidirectional power transmission are its obvious advantages. However, in the pulse frequency modulation control under light-load conditions, the converter will have the disadvantages of output voltage imbalance and low transmission efficiency. In order to improve the range of voltage regulation and efficiency of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLLC</i> resonant converter under light-load conditions, a novel phase-shift pulsewidth modulation method is proposed in this article. There is low voltage gain regulation and low operation losses can be achieved under light load. Considering the parasitic parameters and dead time of the switches, the voltage gain of the proposed control method under light load is precise research by using the time domain analysis method. Finally, an experimental prototype of a bidirectional full-bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLLC</i> resonant converter with 200 V input voltage, 200 V output voltage, and a rated power of 800 W is designed. According to the simulation and experimental results, it can be shown that the proposed control method is effective under light-load operation.

Soft-Switching Full-Bridge DC-DC Converter with Energy Recovery Capacitor Snubber

This paper describes a high-frequency soft-switching dc-dc converter with a simple energy recovery capacitor snubber on the secondary side. The presented dc-dc full-bridge converter with the energy recovery snubber removes the main drawbacks of the classic Phase Shifted PWM (PS-PWM) dc-dc converter, e.g., the circulating current flowing during the free-wheeling interval and dependency of the soft switching on the load current. The converter utilizes a full-bridge topology with pulse-width modulation and a centre-tapped full-wave controlled rectifier with one active switch. The zero-voltage switching on the primary side is ensured by utilising only the magnetizing current of the high-frequency transformer, and thus is load-independent. The proposed energy recovery snubber is described in detailed time waveforms of the converter and verified by simulation. The control algorithm also removes the circulating current, which is typical for PS-PWM converters. The soft-switching of the secondary side transistor is achieved by a simple capacitor snubber with an energy-recovery circuit connected to the output of the dc-dc converter. The principle of operation is verified by measurements on a 2 kW, 50 kHz laboratory model of the proposed dc-dc converter.

A Combinational Level-Shifted and Phase-Shifted PWM Technique for Symmetrical Power Distribution in CHB Inverters

In cascaded H-bridge (CHB) multilevel inverters (MLIs), phase-shifted pulse width modulation (PSPWM) and level-shifted pulse width modulation (LSPWM) are the two prominent techniques to attain multilevel and better performance. But both of them have certain drawbacks like in PSPWM the switching loss of all the semiconductors is high, and in LSPWM the power-sharing between the cascaded modules is not identical. These two drawbacks have been addressed in this article by proposing a novel modulation technique, named the phase opposed disposed phase-shifted PWM (PODPSPWM). In this technique, the level-shifted carriers have been rotated in such a way that there should not be any active power loss and simultaneously the carriers are phase-shifted as per the PSPWM technique. A detailed mathematical analysis of switching loss for all three methods has been presented. Moreover, the power-sharing and harmonic spectrum of the proposed PODPSPWM over other PWMs have been discussed. This novel modulation technique has been simulated in the MATLAB/Simulink software to validate the superiority of the operation. The 1.5-kW experimental prototype is developed to validate the performance of the proposed PODPSPWM modulation.

A Split-Inductor Flying Capacitor Converter for Medium-Voltage Application

This article presents a split-inductor flying capacitor (SIFC) converter for medium-voltage applications to improve reliability and eliminate the shoot-through issue. Reliability and lower total harmonic distortion (THD), mainly caused by the pulsewidth modulation (PWM) dead time, are the vital aspects while designing higher power density converters. The dead time in the PWM can be reduced/removed in the proposed converter. This will increase the voltage/current gain and enhance the quality of the voltage/current waveforms even at lower modulation index and light loads than the traditional flying capacitor (FC) and neutral point clamped (NPC) converters. Furthermore, an improved phase-shifted PWM (IPS-PWM) is used to maintain the flying capacitor’s nominal reference voltage. A comparison is made between SIFC and five different existing multilevel topologies. The proposed converter has higher voltage/current gain, lower THD over conventional FC and NPC converters, and higher efficiency than the other three topologies. Finally, the SIFC converter’s robustness with IPS-PWM is validated using experimental results in different operating conditions such as sudden load changes, modulation index, output frequency, and power factor (unity, lagging, and leading).

An Optimized Carrier Phase-Shifted Modulation Strategy for Cuk PV Inverter

There exists the problems of output voltage zero-point drift and high even harmonic content of the three-phase Cuk liftable voltage photovoltaic (PV) inverter when it adopts the conventional carrier modulation method. In view of these, a new optimized Phase-Shifted Pulse Width Modulation (PSPWM) strategy is proposed. Firstly, the optimal zero-sequence component is determined based on the inverter topology and control objectives. Next, the zero-sequence component is injected into the sinusoidal signal and used as the new modulating signal so that the carrier pulse width modulation is equivalent to the space vector pulse width modulation. Finally, the carrier and modulating waveforms are blended in a superior manner, and a new logical operation is applied to generate the required switching drive signals for the control of the inverter switching tubes. In order to verify the effectiveness of the strategy, simulation and experimental platforms were constructed, and numerous simulations and experiments were done. The results show that the modulation strategy can solve the output voltage zero drift problem effectively, and suppress the even harmonics effectively, meanwhile, the harmonics are mainly concentrated near the primary frequency, which significantly reduces the total harmonic content and greatly improves the output voltage waveform. In addition, the modulation can be achieved by reducing one carrier signal, thus simplifying the modulation process and the design of the digital signal system.

Two Compact Three-Phase Multilevel Inverters for Low-Voltage Applications

In this article, two compact three-phase multilevel inverters are proposed. The first proposed topology consists of three dc sources and ten power switches. The merit of the first proposed topology is reducing two switches from its structure to the conventional topologies. The second proposed topology is similar to the first one, except that one of the dc sources is replaced by a capacitor. This capacitor is balanced by an additional switch and one of the dc sources. How to apply two modulation methods for these inverters has been studied in detail. These modulation methods are level-shifted pulsewidth modulation and phase-shifted pulsewidth modulation (PS-PWM). Also, the value of the capacitor for each of the modulation methods has been calculated. Finally, the experimental results are provided to confirm the performance of the proposed topologies.

Dead-Time Impact on the Harmonic Distortion and Conversion Efficiency in a Three-Phase Five-Level Cascaded H-Bridge Inverter: Mathematical Formulation and Experimental Analysis

To avoid leg short-circuit in inverters, dead time must be introduced on leg gate signals. Dead time affects the inverter output voltage fundamental harmonic amplitude, voltage harmonic distortion and inverter efficiency by introducing additional voltage drops. In this regard, dead time effects have been widely investigated for traditional two-level three-phase voltage source inverters in the literature but not extensively for multilevel topology structures. This paper provides a detailed analysis of dead time impact on the harmonic distortion and efficiency of Cascaded H-Bridges Multilevel Inverters (CHBMIs). For this purpose, a general mathematical formulation to determine voltage drop due to dead time effects, also taking into account the adopted Multicarrier PWM strategy, has been provided and experimentally validated for a five-level three-phase CHBMI structure. As a comparison tool between expected and ideal inverter output voltage, the percentage voltage error <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> % is introduced. In most of the cases, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> % is lower than 5%, and it starts increasing for very low amplitude modulation index or for specific working points where nonlinearities occur. Furthermore, several experimental investigations have been carried out to evaluate the CHBMI performance in terms of harmonic distortion and efficiency by changing, the values of dead time, modulation index and switching frequency for ten different multi-carried PWM strategies. Experimental results confirm the strong dependency between the dead time impact on the converter performance and the adopted Multi Carrier-PWM (MC-PWM) strategy: as a way of example, converter efficiency can be reduced from 80% to 60% when dead time is increased from 0.5 μs to 1.5 μs and Phase Shifted-PWM (PS-PWM) is adopted.

Carrier Redistribution Pulsewidth Modulation for Five-Level Stacked Multicell Converter

This article presents a modified carrier redistribution pulsewidth modulation (CRPWM) method for the five-level stacked multicell converter (SMC). The proposed CRPWM method is modified by exchanging the arrangement of the carriers of phase disposition pulsewidth modulation (PDPWM). With the ingenious carrier arrangement, the proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of each floating capacitor during one switching period of all the switches. The proposed modulation strategy has the same harmonic performance of line-to-line voltage with PDPWM, while the switch utilization is the same as phase-shifted pulsewidth modulation (PSPWM). Therefore, the voltage balancing of floating capacitors is achieved during a minimum switching period even with the influence of load current change and inappropriate carrier ratio is considered. The modified CRPWM is analyzed in theory and the voltage balancing ability and output harmonics performance are compared with PSPWM and traditional CRPWM. Simulation and experimental results on the laboratory prototype five-level SMC confirm the validity of the proposed CRPWM technique.