Phase Noise Figure Research Articles

An impedance matching section based on composite right/left‐handed transmission line model in viewpoint of phase shift and noise figure

AbstractIn this paper, a genetic‐based synthesis approach for an impedance matching section based on a composite right‐/left‐handed (CRLH) transmission line model called CRLH transmission line impedance matching section (CRLHTLIMS) in viewpoint of transmission phase shift and noise figure is newly presented. To find the unknown values of right‐/left‐handed inductances and capacitances of a CRLHTLIMS, a type of global optimization algorithm called continuous parameter genetic algorithm is used. The length, transmission phase shift, and noise figure of the CRLHTLIMS are computed by using simple equations. Different examples for a uniform CRLHTLIMS are given. According to the results, this approach is an easy and effective way for the synthesis of transmission line impedance matching sections in viewpoint of transmission phase shift and noise figure.

Linear Voltage Controlled Oscillator Implementation in Electronically Variable Immittances

New realization schemes of electronically tunable inductor (L) and Frequency-Dependent Negative Resistance (D) type immittances using a Current Feedback Amplifier (CFA) and Multiplication Mode Current Conveyor (MMCC) composite active building block (ABB) are proposed. Applications of the immittances to the design of selective filters and LC-type linear voltage controlled quadrature oscillator (LVCQO) are presented. Experimental results based on PSPICE simulation and hardware design for a linear range of oscillation frequency (fo ~ 13.6MHz) with satisfactory phase-noise figure on the oscillator wave response had been verified. Effects of the Active Building Block (ABB)-nodal imperfections are analyzed to be insignificant. The new ideas in this article are two types of immittance functions realizable in the same topology; appropriate frequency-domain selective responses are also presented with experimentation results.

A Linear VCO Using Single CFA and Analog Multipliers: Quadrature Oscillator Implementation

A new linear voltage-controlled oscillator (LVCO) implementation using single AD-844 CFA with a pair of AD-835 multiplier devices and a pair of grounded capacitors is proposed. The open-loop transfer function of the topology is analyzed wherein the concept of Short-Circuit Natural Frequency (SCNF) is applied to derive the sinusoid oscillator implementation. The proposed oscillator circuit is then restructured to yield a linear voltage-controlled quadrature oscillator (LVCQO) after appropriate cascade with a CFA-based active integrator. The oscillation frequency is linearly tunable ([Formula: see text][Formula: see text]MHz) by the multiplier control voltage ([Formula: see text]. Subsequently, a high-[Formula: see text] selective band-pass (BP) filter is derived. Effects of the CFA port roll-off parameters and its parasitic capacitors ([Formula: see text] had been analyzed to be negligible. Measured oscillator response exhibited a THD [Formula: see text]%, a linearity error ([Formula: see text]% and a phase noise figure of ([Formula: see text]104 dBc/Hz at 24-kHz offset.

An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS

This article presents an ultra-low-noise differential relaxation oscillator that achieves a phase noise figure of merits (FoMs) of 157.7 and 162.1 dBc/Hz, respectively, at 1- and 100-kHz frequency offsets. The oscillator is inherently robust against $1/f$ noise, while swing-boosting minimizes the phase noise arising out of thermal noise. Furthermore, an inverter-based differential comparator maximizes power efficiency, enabling FoMs close to the fundamental limits. Operating at 10.5 MHz and consuming 219.8 $\mu \text{W}$ from a 1.4-V supply, the oscillator achieves a period jitter of 9.86 psrms, equivalent to a relative jitter of 0.01%. The oscillator occupies an active area of 0.015 mm2 in a 0.18- $\mu \text{m}$ standard CMOS process.

A CMOS Frequency Doubler from the Analog Cosine Mapping Function

This work presents the design of a new frequency doubler by a simple inductorless active network, without the exigency of additional quadrature signals. The frequency doubling function of the proposed circuit relies on the analog cosine mapping operation. The mapping circuit is possible in voltage mode as the circuit is based on two face-to-face CMOS inverters switched by the same differential input signal. The circuit is designed, with a simple set of functions, according to the nonlinear circuit’s nature. It was designed in a CMOS 0.18- $$\upmu $$ m process with a doubling frequency up to $$8~\text{ GHz }$$ . The experimental results of the prototype on the mentioned frequency range show the frequency doubling operation with a phase noise figure of $$-\,130~\text{ dBc/Hz }$$ @ $$10~\text{ KHz }$$ offset from the carrier.

Phase evolution of the direct detection noise figure of a nondegenerate fiber phase-sensitive amplifier

We experimentally investigate the evolution of the direct detection noise figure of a nondegenerate phase-sensitive amplifier based on a nonlinear fiber, as a function of the relative phase between the signal, idler, and pump, all other parameters remaining fixed. The use of a fiber with a high stimulated Brillouin scattering threshold permits us to investigate the full range of phase-sensitive gain and noise figure without pump dithering. Good agreement is found with theory, both for signal only and combined signal and idler direct detections.

Low <inline-formula> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math> </inline-formula> Phase Noise Quadrature LC VCOs

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher $1/f^{3}$ phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capacitive paths from the drains of the switching transistors are proposed to make the switching transistors inject noise twice in a cycle and reduce the average ISF to nearly zero. The proposed SQVCOs have a phase noise figure of merit(FoM) close to that of a single-phase VCO for a given tank. They also eliminate mode ambiguity usually present in the coupled VCOs. The 2.4 GHz prototypes of two of the proposed SQVCOs in a 0.13 $\mu \text{m}$ CMOS process have $1/f^{3}$ phase noise corners of 400 and 150 kHz compared to 3 MHz in the conventional SQVCO. At 1 MHz/3 MHz offset, the proposed SQVCOs have measured phase noise(FoM) of −133.5/−145.1 dBc/Hz (188.2/190.2 dB) and −130/−140.2 dBc/Hz (192.5/193.2 dB) whereas the conventional SQVCO has −125.5/−137.6 dBc/Hz (180.3/183 dB). The average measured phase error over five chips is 0.9°.

An Efficient High-Power Fundamental Oscillator Above $f_{\max }/2$ : A Systematic Design

A novel approach to design efficient high-output-power fundamental oscillators beyond $f_{\max }/2$ of the employed process is presented. The idea is to shape and maximize the unilateral power gain ( $U$ ) of the network at the desired frequency using optimum passive internal and external feedback networks. The proposed technique significantly improves the output power and dc-to-RF efficiency of the oscillator. To show the feasibility of this novel approach, a 175 GHz fundamental oscillator is designed in a 130 nm SiGe BiCMOS process ( $f_{\max }\simeq ~280$ GHz), which achieves a measured dc-to-RF efficiency of 11.7% that is markedly higher than all reported oscillators above $f_{\max }/3$ of their active device. Measurements show that the designed oscillator generates a peak power of 3 mW (4.8 dBm) with a phase noise figure of merit (FoM) of −195.4 dBc/Hz at 1 MHz offset frequency, which is the highest phase noise FoM among all reported CMOS/BiCMOS millimeter-wave and terahertz oscillators. The proposed method considers the possible process, voltage, temperature variations as well as modeling errors of the passive components in the design stage.

High-resolution wide-band LC-VCO for reliable operation in phase-locked loops

This paper presents a novel sizing scheme to implement the array of switches in the capacitor bank of LC-VCOs for oscillation frequency coarse control. The proposed scheme allows increasing the number of elements in the capacitor bank beyond the values typically achieved by binary scaling, endowing the resulting LC-VCO with a wider tuning range and high frequency resolution, which is beneficial for the implementation of reliable phase-locked loops. Two different gigahertz LC-VCOs have been designed to validate the proposed scheme. The prototypes, fabricated in a cost-effective 0.18μm CMOS process, cover a 700MHz frequency range from 1.35GHz to 2.05GHz and from 2.05GHz to 2.75GHz, respectively, with a phase noise figure of −122dBc/Hz and −119.5dBc/Hz at 1MHz from the mid-range carriers, and a power consumption of 18mW. These figures result in a respective FOMT of −186.4dBc/Hz and −183.8dBc/Hz. The performance of the fabricated LC-VCOs is achieved in each case with a dense coarse tuning range of 128 levels, which allows, respectively, a fine tuning gain smaller than 40MHzV−1.

Magnonic crystal as a delay line for low-noise auto-oscillators

It is demonstrated that a delay line based on a one-dimensional magnonic crystal used in a feedback loop of a microwave auto-oscillator can substantially reduce the phase noise figure and improve other vital performance characteristics of the auto-oscillator. The advantage is achieved due to the increase of the effective delay time in the magnonic crystal, compared to the case of an un-patterned yttrium iron garnet (YIG) film, and improvement of the power-handling characteristics due to the now possible increase of the YIG film thickness. The internal modes of a magnonic crystal caused by the periodic energy exchange between the incident and reflected spin waves play the dominant role in the described effect.

Design of low power low phase noise negative resistance Ku‐band VCO using planar resonator pair

ABSTRACTNew negative resistance voltage‐controlled oscillator (VCO) at Ku‐band is designed. The proposed topology uses packaged NPN Silicon Germanium RF transistor and two parallel resonator structures connected to the device emitters. Novel active open ended planar structure is proposed as a resonator for the VCO. Resonator is analyzed in terms of required reflection coefficient and input impedance. Resonator's quality factor varies in between 159 and 235 as a function of tuning voltage. VCO microwave IC is fabricated on TMM10i soft substrate with 17.5μm Cr‐Cu‐Au metallization process. VCO can be tuned for 180MHz by varying resonators’ varactors from 0 to 22 V. Measured output power remains in between 4.2 and 8.06 dBm for the entire tuning range. Measured phase noise is −145 dBc/Hz at 1 MHz offset with 8 V tuning voltage. Normalized phase noise figure of merit for the VCO is −214.4 dBc/Hz. The circuit has low power consumption of 25.5 mW and high DC to RF conversion efficiency (ηDC‐RF). © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1938–1941, 2015

Low voltage low-phase-noise SB-QLCO using second harmonics coupling technique

A switched biasing quadrature oscillator with LC tanks (SB-QLCO) is proposed to achieve low voltage and low phase noise. In this work, coupling devices, capacitors, don’t contributes any noise and this second harmonics coupling technique leads to low voltage. The proposed QLCO was simulated in 0.18 μm CMOS process. Simulating results showed a phase noise of −126 dBc/Hz at an offset of 1 MHz and a phasenoise figure of merit of 193 dB while consuming 6 mA from a 0.8 V power supply.

Low Phase Noise GaN HEMT Oscillators With Excellent Figures of Merit

This letter presents guidelines for the design of low phase noise oscillators in GaN high electron mobility transistor (HEMT) technology. The design starts from bias-dependent low-frequency (LF) noise measurements. Oscillator topology and bias point are then chosen for operation in regions where LF noise is low. The best LF noise properties are obtained for low drain voltage and current. Thus, the low phase noise can be achieved at low dc power which also means that power normalized phase noise figure of merit (FOM) will be good.

Implications of I/Q Imbalance, Phase Noise and Noise Figure for SNR and BER of FSK Receivers

In energy-constrained applications like Body Area Networks (BAN) receiver performance is traded for lower power consumption. The limited receiver performance will deteriorate the output signal-to-noise-ratio (SNR) and bit-error-rate (BER) of the receiver. In this paper we present closed-form output SNR and BER models of a non-ideal receiver front-end with limiter-discriminator demodulator for binary FSK. The presented model is very useful in defining the minimally required receiver specifications. Moreover, the models are useful for gaining insight into the influences of the receiver impairments on its performance. In the models, the gain and phase imbalances between the in-phase and quadrature-phase paths as well as the receiver generated noise and the phase noise produced by the local frequency reference are taken into account. This paper shows that the gain and phase imbalances shift the FM threshold to higher carrier-to-noise-ratios (CNR) and only have small influence on the SNR above threshold. On the other hand, receiver generated noise reduces the output SNR both below and above the FM threshold, and phase noise limits the maximum output SNR. Additionally, a trade-off between the FSK frequency deviation and phase noise robustness is derived.

An 11 GHz low‐phase‐noise voltage‐controlled oscillator

PurposeThe purpose of this paper is to design a low phase noise and high figure of merit, fully integrated, voltage‐controlled oscillator (VCO) which was fabricated in TSMC CMOS 0.18‐μm 1P6M process.Design/methodology/approachA differential PMOS cross‐coupled architecture VCO with the capacitive feedback technology was designed to increase the linearity of frequency tuning range and decrease the phase noise. Varactor determining the performance of tuning range is also a key component in the design of VCO. The authors adopt the accumulation‐mode MOS varactor. The output spectrum and the phase noise are measured by E5052A spectrum analyzer.FindingsThe VCO is successfully fabricated in TSMC RF CMOS 0.18um 1P6M process. The measured tuning range is from 10.875 GHz ∼ 11.1 GHz with control voltage from 0 to 1.5 V. The measured phase noise is as low as −120.42 dBc/Hz at 1 MHz offset and the high FOM is −189.5 dBc/Hz. The output spectrum is −10.51dBm with center oscillator frequency of 10.942 GHz. The core circuit without buffer consumes power of 15 mW from a 1.8 V supply voltage.Originality/valueThis paper shows a fully integrated CMOS LCVCO architecture using capacitive feedback technology with low phase noise and high figure of merit for OC‐192 SONET applications.

Oscillator with High Harmonic Suppression Using Split Quarterwave Microstrip Resonator

This letter presents a new type of resonator, namely, the split quarterwave microstrip resonator (SQMR), to improve the poor harmonic suppression and low Q-factors in conventional quarterwave microstrip resonators. An oscillator incorporating the proposed SQMR is designed, fabricated, and tested to demonstrate that, not only the second harmonic suppression, but also the phase noise of the oscillator can be improved. The oscillator with the SQMR shows improved second harmonic suppression of –74.59 dBc and phase noise figure of merit of –169.77 dBc/Hz at 1 MHz offset.

A 66 $\mu$W 86 ppm$/^{\circ}$C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM

This paper presents the design of a new Wienbridge topology. Its phase noise performance, low temperature dependency and low power consumption make it suitable for use in wireless sensor nodes and time-based sensor readout circuitry. The noise as well as temperature behavior of the oscillator is explained using extensive calculations. Measurements on 7 samples of the same batch show a temperature stability of 86 ppm/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C and a measured spread of 0.9% at an oscillation frequency of 6 MHz. The circuit consumes 66 muW and is realized in a 65 nm technology measuring 150 mum by 200 mum. The measured phase noise figure of merit is 172 dB at a frequency offset of 100 kHz.

A Magnetically Tuned Quadrature Oscillator

Continuous frequency tuning by control of the magnetic field of a transformer - capacitor tank, in a selective oscillator, is explored in this work. A quadrature generator is built connecting two identical transformer - capacitor oscillator cells in a feedback loop. The topology itself assures the currents in the transformer windings are aligned in phase, while their relative amplitude determines, via magnetic coupling, oscillators' tank reactance, i.e., oscillation frequency. This paper introduces the idea, analyzes oscillation amplitude, frequency tuning band, phase noise, and phase accuracy, and discusses design and experiments. Prototypes, realized in 65 nm CMOS, employing MOS varactors to further extend operation bandwidth, show the following performances: 3.2 GHz and 7.3 GHz minimum and maximum oscillation frequency, respectively. Phase noise figure of merit of 176.5 dB at 3.2 GHz and 170.5 dB at 6.4 GHz is observed, with 24 mW maximum power consumption and 1.5 maximum deviation from quadrature.

A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy

Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-mum CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (IBR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB