Phase-locked Loop Synthesizer Research Articles

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

АНАЛИЗ ПЕРЕХОДНЫХ ПРОЦЕССОВ В СИНТЕЗАТОРАХ ЧАСТОТ С РАЗЛИЧНЫМИ ХАРАКТЕРИСТИКАМИ НЕЛИНЕЙНОГО ЗВЕНА В КОНТУРЕ ФАЗОВОЙ АВТОПОДСТРОЙКОЙ ЧАСТОТЫ

Phase-locked loop (PLL) frequency synthesizers that use phase detectors (PD) with variousnonlinear transfer characteristics have been considered. The goal of this work is comparative analysisof the frequency synthesizers operation speed depending on the type of the PD nonlinearity andmathematical description of the PD nonlinear characteristic which ensure the maximum operationspeed of the frequency synthesizer. In accordance with the present goal, the following problems aresolved in this work: the generalized model of the PLL frequency synthesizer is developed; mathematicalmodels of static characteristics of the PLL system nonlinear link are described when using varioustypes of known PDs and a modified PD with aperiodic characteristic; the analysis of the PLLsystem dynamics when changing the static characteristic of the nonlinear link is carried out. Themodified PD provides relay control of transient processes when a large phase difference occurs.Numerical evaluation of the PLL synthesizers operation speed depending on the initial frequencydeviation have been obtained when using known PDs and the modified PD. It is shown that the use ofthe modified PD allows to reduce frequency settling time about 1.5 times in comparison with the bestin operation speed conventional PD. Optimal values of the control signal ensuring the maximumoperation speed of the PLL synthesizer with the modified PD have been obtained for the specifiedfrequency deviations in the large disturbance mode. The results of this work are valid for PLL frequencysynthesizers of the UHF, L, S and C-bands (from 300 MHz to 8 GHz) which are used in wirelesscommunication systems of the fourth generation (4G) and the fifth generation (5G).

A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands.

Design and Verification of a Q-Band Test Source for UAV-Based Radiation Pattern Measurements

In the last years, the unmanned aerial vehicles (UAVs) generated significant innovations in in situ antenna measurements. UAV-mounted test sources have been exploited to characterize the radiation pattern of receiving antennas and arrays for HF radars, radio telescopes in very high-frequency (VHF) band, and up to the X-band for radar characterization. A UAV test source operating in the Q-band has been recently developed within the large-scale polarization explorer (LSPE) project. It will be used for the in situ validation of a ground-based cluster of coherent polarimeters for cosmology observation. This article presents the payload solution that is actually applicable to general UAV-based radiation pattern measurements in the Q-band. It is based on a phase-locked loop synthesizer and an active multiplier coupled with a power detector to compensate for signal power drifts in postprocessing. Relevant system tests have been performed in both laboratory environment and operative conditions. The measured outdoor radiation patterns are in good agreement with both the anechoic chamber measurements and simulated data.

Phase Noise Effect on Millimeter-Wave Pre-5G Systems

The introduction of millimeter waves for 5G wireless communication systems enables the use of more bandwidth and higher carrier frequency, surpassing the capacity of current systems by more than one order of magnitude. The leap of millimeter band results from the development of analog frontends that unfortunately induce relatively large phase noise in phase-locked loop synthesizers. Large phase noise may generate considerable random phase error and residual frequency offset, which in turn produces additional phase error. We evaluate phase error from phase noise on an implemented pre-5G system operating in the millimeter band and through a simulation by modeling the characteristics of a radio frequency integrated circuit. We measure and then compare the residual frequency offset, phase error, and error vector magnitude between the experimental and simulation results. We verify that the phase noise model suitably approximates to the real conditions. Moreover, we show that phase error remains at approximately 4° in the implemented system. By exploiting the implemented phase error compensation, our pre-5G system can overcome a degradation of 1.5 dB in error vector magnitude and achieve an approximate transmission rate of 4 Gbps at gain of 1.49.

A Dielectric Constant Measurement System for Liquid Based on SIW Resonator

A self-sustained dielectric constant (i.e., permittivity) measurement system for liquid is proposed. A tunable substrate integrated waveguide (SIW) resonator is exploited to form a feedback-type voltage controlled oscillator (VCO) that is further embedded into a phase locked loop (PLL)-based frequency synthesizer. The SIW resonator acts as the feedback element of the VCO. When the SIW resonator is exposed to liquid, its frequency response and the corresponding VCO oscillation frequency change accordingly because of electromagnetic field perturbation. Due to the presence of the PLL, the eventual frequency of synthesizer is kept constant, while this potential frequency shift is translated into the output voltage of the PLL loop filter. This voltage is readily measured by a digital multi-meter. Principles and design considerations of the SIW resonator as well as implementations of the VCO and the PLL synthesizer are discussed in detail. In addition, a prototype sensing platform is devised. Correlations between the dielectric constant of liquid MUT and the physical parameters, such as the SIW resonant frequency, the VCO oscillation frequency, and the PLL output voltage are analyzed comprehensively. According to the experimental results of several organic liquids, the proposed system can achieve an accuracy better than 4% for permittivity characterization.

A fully integrated CMOS 60-GHz transceiver for IEEE802.11ad applications

A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology. The reported transceiver monolithically integrates a receiver, transmitter, PLL(Phase-Locked Loop) synthesizer, and LO (Local Oscillator) path based on a sliding-IF architecture. The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel, with an EVM (Error Vector Magnitude) of lower than −20 dB. The receiver path achieves a configurable conversion gain of 36∼64 dB and a noise figure of 7.1 dB over 57∼64 GHz, while consuming only 177 mW of power. The transmitter achieves a conversion gain of roughly 26 dB, with an output P1dB of 8 dBm and a saturated output power of over 10 dBm, consuming 252 mW of power from a 1.2-V supply. The LO path is composed of a 24-GHz PLL, doubler, and a divider chain, as well as an LO distribution network. In closed-loop operation mode, the PLL exhibits an integrated phase error of 3.3° rms (from 100 kHz to 100 MHz) over prescribed frequency bands, and a total power dissipation of only 26 mW. All measured results are rigorously loyal to the simulation.

A Proximity Coupling RF Sensor for Wrist Pulse Detection Based on Injection-Locked PLL

In this paper, a proximity coupling RF sensor based on injection-locked phase-locked loop (PLL) for wrist pulse detection is proposed. The sensor is composed of two main parts: a free-running oscillator and a PLL synthesizer containing a voltage-controlled oscillator. The free-running oscillator is built with a two-port microstrip line resonator (inter-digital electrodes), which acts as part of a transducer that can transform the expansion or contraction of the radial artery into an impedance variation. Measurements show that the impedance variation of the resonator due to changes in the radial artery causes a frequency change of up to 0.74 MHz in the free-running oscillator. For the PLL part, the frequency change can be transformed to a variation in dc voltage by injection of the modulated signal from the wrist pulse into a phase-locked oscillator. The variation of the loop-control voltage, in one cycle of the pulse, is approximately 10–15 mV peak-to-peak. Our sensor is demonstrated to be an effective noncontact and noninvasive scheme for wrist pulse detection.

High-Performance E-Band Transceiver Chipset for Point-to-Point Communication in SiGe BiCMOS Technology

Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13- $\mu{\hbox{m}}$ SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than $-{\hbox{12-dBm}}$ input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71–76 GHz) and higher band (HB) (81–86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission.

Development of High-performance Microwave Water Surface Current Meter for General Use to Extend the Applicable Velocity Range of Microwave Water Surface Current Meter on River Discharge Measurements

To overcome the difficulties of discharge measurements during flood season, MWSCM(micowave water surface current meter) which measures river surface velocities without contacting water has been applied in field work since its development. The existing version of MWSCM is for floods so that its applicability is low due to the short periods of floods. Therefore the renovative redesign of MWSCM to increase the applicability was conducted so that it can be applied to the discharge measurements during normal flows as well as flood ones by extending the measurable range of velocity. A newly developed high-performance MWSCM for general use can measure the velocity range of 0.03-20.0 m/s from flood flows to normal flows, whereas MWSCM for floods can measure the velocity range of 0.5-10.0 m/s. The improvement of antenna isolation between transmitter and receiver to block the inflow of transmitted singals to receiver and the improvement of phase noise of oscillator are necessary for detecting low velocity with MWSCM technology. Separate type antenna of transmitting and receiving signals is developed for isolation enhancement and phase locked loop synthesizer as an oscillator is applied to high-performance MWSCM for general use. Microwave frequency of 24 GHz is applied to the new MWSCM rather than 10 GHz to make the new MWSCM small and light for convenient use of it at fields. Improvement requests on MWSCM for floods-stable velocity measurement, self test, low power consumtion, and waterproof and dampproof-from the users of it has been reflected on the development of the new version of MWSCM.

Estimation of break-lock in PLL synthesizers for monopulse radar applications: Experimental and simulation approach

This work presents and estimates the break-lock in phase locked loop (PLL) synthesizers for monopulse radar applications through experimental measurements and computer simulation. Sinusoidal continuous wave (CW) and linear frequency modulated (LFM) signals are used as repeater jamming signals. The CW jamming signal power as a function of radar echo signal power at break-lock is estimated for different values of frequency difference between these two signals, and from these results the jammer to echo signal power (J/S) ratio (in dB) is computed. Break-lock is achieved at a J/S ratio of 1.9 dB (measured at 1.8 dB) for a typical echo signal power of −5 dBm with a 1 MHz frequency difference. The frequency deviation as a function of J/S ratio required to break-lock is estimated for different modulation rates in the presence of LFM jamming signal. Break-lock is achieved at a frequency deviation of 0.34 MHz (measured at 0.32 MHz) for a J/S ratio of 2 dB and 200 kHz modulation rate. The simulation models are proposed accordingly to the data obtained from the experimental setups. Good and consistent agreements between the measured and simulated results are observed and can be useful in the design of CW and LFM jammers in the target platform.

An Ultra-Low Phase-Noise 20-GHz PLL Utilizing an Optoelectronic Voltage-Controlled Oscillator

This paper describes a novel phase-locked loop (PLL) architecture utilizing an optoelectronic oscillator (OEO) as a voltage-controlled oscillator (VCO). The OEO demonstrates excellent far-out phase-noise performance while the PLL reduces the close-in phase noise. The nonmonotonic VCO characteristics of the OEO placed stringent demands on the loop filter electronics and startup conditions. The crystal reference, prescalar, frequency synthesizer, and loop filter were all implemented with discrete high-performance components. The resulting frequency synthesizer yields a -10-dBm output at 20 GHz with phase noise of -80 dBc/Hz at 100-Hz offset, and -134 dBc/Hz at 10-kHz offset. These results are far superior to PLL synthesizers utilizing only an electronic VCO and illustrate the power of optoelectronic integration.

An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology

This paper presents an X-band chirp radar transceiver with bandwidth reduction for range detection. The radar transceiver includes a super-heterodyne receiver including an ADC, a direct-digital synthesizer (DDS) based transmitter and a phase-locked loop (PLL) synthesizer. In a modified Weaver architecture, the down-converted baseband signal is further mixed with another chirp signal through stretch processing. The resulting waveform bandwidth is greatly reduced and thus relaxes the power and bandwidth requirements of the on-chip ADC. Therefore, the proposed radar transceiver achieves power and bandwidth reductions without degrading its range resolution. The radar-on-chip (RoC) MMIC was implemented in a 0.13 µm SiGe technology with die area of 3.5 × 2.5 mm 2 . With a 2.2 V supply for analog/RF circuits and a 1.5 V supply for the digital portion, the chip consumes 326 mW in the receive mode and 333 mW in the transmit mode, respectively.

Design of a programmable CMOS Charge-Pump for phase-locked loop synthesizers

A charge pump circuit capable of operating at different switching speed is presented. The switching speed control is added to a typical charge pump circuit by mean of enable switches which allow drive different currents. Charge pump circuit is implemented in AMI 0.5μm CMOS technology. Simulations were performed using Spectre from CadenceTM. Simulation results show clearly an increase in the slope of charging or discharging curves of load capacitor during the pumping-up and pumping-down phases.

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18 μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μA and a precharging current of 70 μA. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications

A 2.4-GHz energy-efficient transmitter (TX) for wireless medical applications is presented in this paper. It consists of four blocks: a phase-locked loop (PLL) synthesizer with a direct frequency presetting technique, a class-B power amplifier, a digital processor, and nonvolatile memory (NVM). The frequency presetting technique can accurately preset the carrier frequency of the voltage-controlled oscillator and reduce the lock-in time of the PLL synthesizer, further increasing the data rate of communication with low power consumption. The digital processor automatically compensates preset frequency variation with process, voltage, and temperature. The NVM stores the presetting signals and calibration data so that the TX can avoid the repetitive calibration process and save the energy in practical applications. The design is implemented in 0.18- μm radio-frequency complementary metal-oxide semiconductor process and the active area is 1.3 mm (2). The TX achieves 0-dBm output power with a maximum data rate of 4 Mb/s/2 Mb/s and dissipates 2.7-mA/5.4-mA current from a 1.8-V power supply for on-off keying/frequency-shift keying modulation, respectively. The corresponding energy efficiency is 1.2 nJ/b·mW and 4.8 nJ/b· mW when normalized to the transmitting power.

Decision-directed phase noise compensation for millimeter-wave single carrier systems with iterative frequency-domain equalization

This paper proposes a receiver that repeats iterative frequency-domain equalization (FDE) and decision-directed phase noise compensation (DD-PNC) to alleviate degradation due to the phase noise for millimeter-wave single carrier (SC) systems. High bit-rate SC-FDE transceivers based on the single-chip Si RF-CMOS IC technology in the 60-GHz millimeter-wave band have been extensively studied for wireless personal area network (WPAN) systems, and the relatively large phase noise in a phase-locked loop (PLL) synthesizer severely degrades transmission performance. In an initial processing of the proposed receiver, a cyclic prefix (CP)-based phase noise compensator (CP-PNC) removes the phase noise from a time-domain received signal by using CP, which is known to the receiver, and the channel is equalized by the iterative FDE using the conventional minimum mean-square-error (MMSE) weight. In an iterative processing, DD-PNC estimates the phase noise each symbol by exploiting an output of a channel decoder, and then compensates the time-domain received signal for the phase noise by using the estimate. In order to equalize the compensated received signal, the iterative FDE performs both the MMSE filtering and residual inter-symbol interference cancelation using the decoder output. Computer simulations following the 60-GHz WPAN standard demonstrate that in the 64QAM with the coding rate of 3/4, the proposed receiver with three iterations can drastically remove the phase noise of −85 dBc/Hz at 1 MHz offset, and that it can achieve excellent transmission performance.

A Rigorous Analysis of a Phase-Locked Oscillator Under Injection

This study presents injection-pulling effects on a local oscillator (LO) for wireless applications. A discrete-time analysis is provided to predict output spectra of the LO pulled by a sinusoidal and angle-modulated injection signal. A phase-locked loop synthesizer with an injection signal is analyzed in frequency domain to account for the inherent bandpass filtering on the injection signal. In addition, a phase noise model is developed by using the proposed frequency-domain approach to characterize the overall phase noise of a phase-locked oscillator under injection. Comparison between theoretical predictions and experimental results shows excellent agreement.

A PLL Synthesizer with Learning Repeatable Fluctuation of Input Signal

This paper describes a high frequency PLL (Phase Locked Loop) synthesizer with a function of learning then eliminating repeatable fluctuation of timing intervals on series input pulses. Typical spindle encoder generates digital pulses according to the revolution speed. The intervals of each pulse have repeatable fluctuation every revolution by eccentricity or warpage of the encoder scale disk. This method provides a programmable counter for the loop counter of PLL circuit and an interval counter with memory in order to learn the repeatable fluctuation. After the learning process, the PLL generates very pure tone clock signal based on the real flutter components of the spindle revolution speed without influenced by encoder errors. This method has been applied to a hard disk test system in order to generate 3GHz read/write clock.