Phase-locked Loop Loop Research Articles

고체형 정밀 공진 자이로스코프를 위한 이차 PLL 루프필터 기반 위상제어루프 설계

This paper suggests a design method of an improved phase control loop for tracking resonant frequency of solid type precision resonant gyroscope. In general, a low cost MEMS gyroscope adapts the automatic gain control loops by taking a velocity feedback configuration. This control technique for controlling the resonance amplitude shows a stable performance. But in terms of resonant frequency tracking, this technique shows an unreliable performance due to phase errors because the AGC method cannot provide an active phase control capability. For the resonance control loop design of a solid type precision resonant gyroscope, this paper presents a phase domain control loop based on linear PLL (Phase Locked Loop). In particular, phase control loop is exploited using a higher order PLL loop filter by extending the first order active PI (Proportion-Integral) filter. For the verification of the proposed loop design, a hemispherical resonant gyroscope is considered. Numerical simulation result demonstrates that the control loop shows a robust performance against initial resonant frequency gap between resonator and voltage control oscillator. Also it is verified that the designed loop achieves a stable oscillation even under the initial frequency gap condition of about 25 Hz, which amounts to about 1% of the natural frequency of a conventional resonant gyroscope.

Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation

During the grid synchronization of distributed generation (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect grid phase angle. Conventional PLL schemes used in DG controller have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To simultaneously realize good steady-state and transient performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored to eliminate any specified harmonic. The proposed DSC operator can be further cascaded to stepwise reject all undesired harmonics. Then the conditioned voltage signal can be used in PLL loop to achieve fast transient response at high control bandwidth without suffering from the steady-state error caused by harmonics. Based on differently configured DSC operators, two PLL designs are then developed, namely CDSC-PLL1 and CDSC-PLL2. Specifically, CDSC-PLL1 is aimed for grid voltage with unbalance and odd/even harmonics, while CDSC-PLL2 further addresses asymmetrical harmonics, i.e., harmonics arising from asymmetrically distorted three-phase voltages. By introducing a frequency feedback loop, the proposed PLL can operate properly during considerable frequency variations, even when a phase jump or severe harmonics are also present. All proposed PLL designs have very simple structure and can be easily implemented. The superior performance is confirmed by experimental results.

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL

Phase-locked loop (PLL) is usually required to detect grid phase angle in grid-tied converters. Conventional PLL schemes have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To overcome this challenge, a generalized delayed-signal-cancellation (DSC) operator is proposed recently to form cascaded DSC (CDSC) operator to eliminate arbitrary harmonics. With the CDSC operator, the conditioned voltage can be used in PLL loop with very high bandwidth for fast tracking. However, for digital implementation, the CDSC operator may subject to delay-time error, which subsequently leads to residual distortions in the conditioned voltage. In this paper, a thorough analysis of the CDSC operator in both synchronous and stationary reference frames is first conducted. The discretization error during digital implementation due to nonideal system sampling frequency and/or grid-frequency variation is quantified with the proposed concept of relative harmonic gain error. An effective improvement method is then developed that is based on linear interpolation and is effective for all delay-based PLL schemes. Finally, experimental results are obtained to verify the harmonic elimination ability of CDSC in various scenarios and the effectiveness of the interpolation-based digital implementation scheme.

A 54–862-MHz CMOS Transceiver for TV-Band White-Space Device Applications

A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">step</sub> variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of >; +6.4 dBm, OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of >; +15.9 dBm, and error vector magnitude (EVM) of <; -34.7 dB for 64-QAM signal. The image and carrier leakage calibration circuits suppress the leakage components below -41 dBc across the entire band. The receiver achieves about 100-dB gain dynamic range, 3.5-6.9-dB noise figure, <; -29-dB EVM, and -43.4/-59.7-dBc third/fifth harmonic mixing suppression. The synthesizer and LO generator achieves the integrated phase noise <; 0.8 rms degree over the entire band.

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from −40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.

Method to suppress DDFS spurious signals in a frequency-hopping synthesizer with DDFS-driven PLL architecture

In this paper we propose a method of removing from synthesizer output spurious signals due to quasi-amplitude modulation and superposition effect in a frequency-hopping synthesizer with direct digital frequency synthesizer (DDFS)-driven phase-locked loop (PLL) architecture, which has the advantages of high frequency resolution, fast transition time, and small size. There are spurious signals that depend on normalized frequency of DDFS. They can be dominant if they occur within the PLL loop bandwidth. We suggest that such signals can be eliminated by purposefully creating frequency errors in the developed synthesizer.

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 A. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 m CMOS technology to employ the proposed capacitor multiplier.

Experimental Analysis of Substrate Noise Effect on PLL Performance

This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise transfer functions. It also leads to the conclusion that the PLL blocks other than the VCO can be more sensitive to substrate noise coupling, depending on the substrate noise frequency. Furthermore, the result shows that intermodulation near the reference clock frequency could be a dominant source of generating sidebands in fractional-N PLLs.

Phase noise and jitter modeling for fractional-N PLLs

Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.

Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter

This paper proposes a Miller capacitor which has a wide input signal range. By discharging the charge of the capacitor connected between the input and output terminals of an amplifier before the output voltage of the amplifier exceeds its maximum range, the amplifier always operates in the active region and the Miller operation can be guaranteed. Thus a large value capacitor with a wide dynamic operation range can be realized using a small value capacitor. The Miller capacitor proposed in this paper is applied to a loop filter of phase locked loop (PLL) circuit that requires a large value capacitor to realize a low cutoff frequency. SPICE simulation of the PLL circuit using the Miller capacitor confirms the operation of the Miller capacitor and shows good performances that are similar to those obtained using a passive capacitor of a large value.

A CMOS 1&amp;lt;tex&amp;gt;$times$&amp;lt;/tex&amp;gt;–16&amp;lt;tex&amp;gt;$times$&amp;lt;/tex&amp;gt;Speed DVD Write Channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.

Methodology for on-chip adaptive jitter minimization in phase-locked loops

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

A phase tracking system for three phase utility interface inverters

The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the three phase utility interface inverters. The dynamic behavior of the closed loop PLL system is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system. In particular, the performance of the three phase PLL system is analyzed in the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by the nonlinear load conditions and measurement errors. The tracking errors under these distorted utility conditions are also derived. The phase tracking system is implemented in a digital manner using a digital signal processor (DSP) to verify the analytic results. The design considerations for the phase tracking system are deduced from the analytic and experimental results.

Phase-locked loop for grid-connected three-phase power conversion systems

Analysis and design of a phase-locked loop (PLL) is presented for the power factor control of grid-connected three-phase power conversion systems. The dynamic characteristics of the closed loop PLL system with a second order are investigated in both continuous and discrete-time domains, and the optimisation method is discussed. In particular, the performance of the PLL in the three-phase system is analysed under the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by nonlinear loads and measurement errors. The PLL technique for the three-phase system is implemented in software of a digital signal processor to verify the analytic results, and the experiments are carried out for various utility conditions. This technique is finally applied to the grid-connected photovoltaic power generation system with the current-controlled PWM inverter as a subpart for generating the current reference of the inverter. The experimental results demonstrate its phase tracking capability in the three-phase grid-connected operation.

A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz

A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-/spl mu/m digital CMOS6S process. The PLL design supports multiple integer and noninteger frequency multiplication factors for both the processor clock and an L2 cache clock. The fully differential delay-interpolating voltage-controlled oscillator (VCO) is tunable over a frequency range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for the maximum VCO frequency range settings is 340-612 MHz. The charge-pump current is programmable for additional control of the PLL loop dynamics. A differential on-chip loop filter with common-mode correction improves noise rejection. Cycle-cycle jitter measurements with the microprocessor actively executing instructions were 10.0 ps rms, 80 ps peak to peak (P-P) measured from the clock tree. Cycle-cycle jitter measured for the processor in a reset state with the clock tree active was 8.4 ps rms, 62 ps P-P. PLL area is 1040/spl times/640 /spl mu/m/sup 2/. Power dissipation is <100 mW.

Low-power dividerless frequency synthesis using aperture phase detection

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLL's loop bandwidth is measured to he 6 MHz, with a reference spurious level of -47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.