Input Of Phase Locked Loop Research Articles

Reduced Order DFIG Models for PLL-Based Grid Synchronization Stability Assessment

This paper presents a reduced-order modeling approach to study the grid synchronization stability of type-3 wind turbine generator (WTG) by considering the dynamics of the phase-locked loop (PLL) alone. The proposed model is validated by comparing its time-domain response and small-signal results with the full-order dynamical model of a type-3 WTG system. Extension of the proposed reduced-order model is shown in a wind farm with N numbers of the WTGs, and time-domain simulations are performed under stable and unstable scenarios. The developed model is further utilized for directly assessing the transient stability of a doubly-fed induction generator-based wind turbine generator (DFIG-WTG) system leveraging Lyapunov's direct method. From the direct transient stability assessment methodology, an approximate estimate of the critical clearing time (CCT) is obtained for the DFIG-WTG system to ensure large-signal stability following severe grid fault. Finally, the parametric conditions are derived theoretically, which can determine the stable and unstable region of operation of the DFIG-WTG system with respect to the PLL parameters, grid impedance, and input wind speed.

Improved Weak Grids Synchronization Unit for Passivity Enhancement of Grid-Connected Inverter

The weak grids may be unstable due to the negative resistance behavior of the grid-connected inverter (GCI) caused by the synchronization unit with the phase-locked loop (PLL). This article proposes a passivity enhancement method to attain the positive output resistance of GCI in the qq channel. Initially, the impedance decomposition is utilized to reveal the reason for the negative output resistance brought by PLL. Secondly, with decomposed impedance, a novel PLL by adding a prefilter and an impedance phase regulator with a normalized amplitude to the input of traditional synchronous reference frame PLL (SRF-PLL) is proposed. Afterward, the effect of the critical system parameters and GCI operating conditions on the GCI’s passivity is discussed based on the established small-signal impedance model. Theoretical analysis manifests that the proposed PLL does not affect the system’s stability under rectifier mode and brings the passivity of GCI’s output impedance in the qq channel in broad system parameters under inverter mode. Lastly, the experiments are implemented, verifying that using the proposed PLL, the instability caused by the intersection between grid and GCI impedances is removed due to the passivity, and the system can operate at 1.0 per unit (pu) active power reference under the very-weak-grid conditions.

An Enhanced Sensorless Control Scheme for PMSM Drives Considering Self-inductance Asymmetry

Inductance asymmetry, which is brought by inherent asymmetric parameters, manufacture tolerance, winding fault, cables with unequal lengths, etc., of permanent-magnet synchronous machines (PMSMs) can cause current harmonics and inaccurate position estimation. This paper proposes an enhanced fundamental model based sensorless control strategy for PMSMs with asymmetric inductances. The proportional-integral-resonant current regulator is introduced to reduce the second-order harmonics of currents, but there are still negative sequence components in the estimated back-electromotive forces (EMFs), which can cause the position estimated error. Differing from conventional methods in which negative sequences are filtered out before the phase-locked loop (PLL) module, the proposed method directly applies the estimated back-EMF with negative sequences as the reference input of PLL. An improved PLL with a bi-quad filter is proposed to attenuate the arising second harmonic position error and heighten the steady-state accuracy. Then, this position error is used for asymmetric inductance identification and its result is utilized to update the observer model. Furthermore, the dynamic performance is improved by the output limitation on the bi-quad filter as well as the implementation of a fast-locking technique in the PLL. The effectiveness of the proposed scheme is verified by experimental results.

Improving Small-Signal Stability of Grid-Connected Inverter Under Weak Grid by Decoupling Phase-Lock Loop and Grid Impedance

The wide bandwidth of phase-locked loop (PLL) will increase the negative real part of the output impedance of the grid-connected inverter (GCI), thus destroying the stability of the weak grids. This article proposes a novel method to improve the system stability through decoupling the PLL and grid impedance. Initially, the coupling relationship between PLL and grid impedance is revealed. It can explain why the choice of PLL bandwidth and the grid impedance magnitude is limited. Then, the decoupling method is proposed where the primary control structure of GCI does not need to change and uses the structured voltage, the product of PCC voltage and grid admittance, as the improved input of PLL. The proposed method can achieve the full-frequency passive of the output impedance of GCI even if the PLL has high bandwidth and the impedance measurement error is up to 60%, which means the adverse stability effect of PLL on the system is eliminated. The theoretical analysis is verified by simulations and experiments.

Impact of PLL Frequency Limiter on Synchronization Stability of Grid Feeding Converter

It is well known that grid-feeding converters that synchronize to the grid through a Phase-Locked Loop (PLL) can become unstable after a fault. An often-neglected element that plays an important role in the converter synchronization stability is the PLL frequency limiter. While it slows down the phase change during the fault, the frequency limiter also constrains the error of the PLL input, thus leading to a longer settling time. This letter investigates the mechanism of the converter synchronization stability caused by the frequency limiter and provides a taxonomy to evaluate its impact on the overall system dynamic response.

An Effective Solution to Eliminate DC-Offset for Extracting the Phase and Frequency of Grid Voltage

Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.

Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT

In single-phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well-known tool for designing advanced phase-locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT-based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half-cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase-locked loop (SRF-PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT-based SRF-PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.

Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations

The presence of the dc component in the phase-locked loop (PLL) input results in fundamental frequency oscillations in the phase and frequency estimated by the PLL. The removal of these oscillations is a challenging task because of their low frequency. The aim of this paper is to provide a detailed analysis of several approaches that little work has been conducted on their application for addressing the problem of dc offset in the PLL algorithms. These approaches include using the dq -frame delayed signal cancellation (DSC) operator and the notch filter (NF) as the PLL in-loop filtering stages, and using the $\alpha \beta$ -frame DSC operator, the complex coefficient filter, and a cross-feedback network for blocking the dc offset before the PLL input. Design aspects of these methods are presented, some methods to enhance their performances are proposed, and their advantages and disadvantages are evaluated.

Effectiveness of Repeat Jamming using Linear FM Interference Signal in Monopulse receivers

Abstract Monopulse technique is widely used in modern tracking radars and missile seekers for precise angle (frequency) tracking. In this paper, the break-lock behavior of phase locked loop (PLL) in monopulse radar receiver in presence of linear frequency modulated (LFM) repeater jamming signal is presented. The radar echo and LFM signals are injected into the PLL simultaneously with an assumption that initially, the PLL locks onto the echo signal frequency. The frequency deviation required for breaking the frequency lock as a function of jamming signal power and modulation rate is reported. The results show that break-lock is achieved at frequency deviation of 0.35 MHz for a typical jammer power of -14 dBm and 200 kHz modulation rate when the radar echo power at the PLL input is -14 dBm. The break-lock is also studied for different modulation rate (200, 300, 400 kHz and so) and echo signal power (-14, -10 dBm) at the input of the PLL. For the computer simulation, the radar echo and centre frequency of LFM signals are assumed at an intermediate frequency (IF) of 50 MHz such that the LFM signal closely replicate the actual radar echo signal. The PLL containing charge pump phase detector and passive loop filter is designed with a typical bandwidth of 200 kHz. The simulation is carried out using visual system simulator AWR software and potential conclusions are demonstrated.

PMSM Control Based on Edge-Field Hall Sensor Signals Through ANF-PLL Processing

To detect the rotor angle of the permanent-magnet (PM) synchronous motor (PMSM), two linear Hall sensors are utilized to measure the fringe field of the PM from one end of the rotor. The measured signals look like sin θ and cos θ but contain large third-order harmonics. To remove the third-order harmonics, an adaptive notch filter (ANF) is utilized. Furthermore, the ANF is closely connected with an orthogonal phase-locked loop (PLL): The ANF eliminates the harmonics from the PLL input, and the PLL output is used for generating the harmonic reference signals that are required by the ANF. That is, the ANF utilizes the PLL outputs in removing the target harmonic components from the PLL inputs. The PLL angle estimates are used for implementing the field-oriented control of a PMSM. Experimental results in the low-speed region look better than the sensorless algorithms. This kind of edge-field detection method is advantageous since it is easy to install and less affected by the stator current, i.e., relatively robust to the armature reaction.