Abstract
Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.
Highlights
Rapid and precise extraction of grid voltage frequency and phase angle is a critical process for grid interactive converters and microgrids [1, 2]
The performance of SRF-PLL is dramatically deteriorated in case of existence of DC-offset on grid voltages. e DC-offset component may occur due to measurement devices, DC injection from generation systems, A/D conversion processes, grid faults, and so on [9]. is component causes fundamental frequency fluctuations in phase angle and frequency measurement
The cross-feedback network, complex-coefficient filter, and αβ-frame delayed signal cancellation (DSC) operator are used in prefilter stage of PLL while the notch filter (NF) and dq-frame DSC operator are used in its in-loop filter stage
Summary
Rapid and precise extraction of grid voltage frequency and phase angle is a critical process for grid interactive converters and microgrids [1, 2]. In [13], five DC-offset removal techniques based on prefiltering and in-loop filtering are analyzed in detail Among these methods, the cross-feedback network, complex-coefficient filter, and αβ-frame delayed signal cancellation (DSC) operator are used in prefilter stage of PLL while the notch filter (NF) and dq-frame DSC (dqDSC) operator are used in its in-loop filter stage. (1) e suggested dqADSC-PLL has a simple structure and is easy to implement (2) Its parameter design process is straightforward because only one parameter has to be set in its structure (3) It considerably reduces the convergence time (4) In addition to effectively blocking the DC-offset component, it minimizes the discretization errors e effectiveness and feasibility of the suggested method are validated by simulation and experimental studies and comparison with standard dqDSC-PLL and NF-PLL, which have the different filters in the loop of the PLL to cancel out the DC-offset disturbance component
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
