Behavior Of Phase-locked Loop Research Articles

Modification over Dithered DPLL to reduce the effect of narrowband channel interference

Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and its modified versions. To overcome the effect of channel interference, a single tone dither signal is included in the loop of DPLL. Although an improvement in acquisition and tracking performance is observed, but addition of dither signal contributes to the phase error variance and consequently output noise to increase. Therefore, a further modification is proposed by incorporating an additional phase control in the digital control oscillator (DCO) of the loop to improve the output SNR. The proposed loop is implemented on reconfigurable logic platform using System Generator, a tool from Xilinx used to design real time DSP application. The hardware simulation results demonstrate a comparison among traditional DPLL, dithered DPLL and phase controlled dithered DPLL where the proposed version of the loop outperforms others in terms of acquisition and noise rejection. Keywords DSP Digital Phase Locked Loop, Phase Controlled DPLL, Channel Interference, Dither DPLL, VHDL System Design, Modified DCO

Overview of SOGI-Based Single-Phase Phase-Locked Loops for Grid Synchronization Under Complex Grid Conditions

Synchronization is the key part to ensure the high performance of grid-connected systems. Phase-locked loop (PLL) is one of the most popular synchronizations due to its simple implementation and robustness under certain grid variations. Particularly, in single-phase applications, PLL based on second-order generalized integrator (SOGI-PLL) is widely used because of its simple structure, certain filtering ability and frequency adaptability. The sensitivity of SOGI-PLL to the dc offset and low-order harmonics has been studied a lot in the literature and many solutions have been proposed. However, as more and more power electronic devices are integrated into the power grid recently, the grid condition becomes more complex. As a result, the nonlinear loop coupling phenomenon of SOGI-PLL is more severe and obvious and thus the performance of SOGI-PLL is degraded a lot, especially under the conditions of grid frequency variations and weak grid. A popular method is to use the frequency-fixed SOGI-PLL (FFSOGI-PLL) while how to eliminate the estimation error under frequency variations remain an important task. Though some scattered methods have been proposed, a simple yet effective strategy is still missing. Besides, it has been shown that the system stability margin will be reduced due to the negative-resistance behavior of PLL. However, the models derived in the current documents cannot accurately reveal the instabilities caused by the standard SOGI-PLL for missing the dynamics of the frequency feedback loop. Moreover, the PLL parameters are usually designed according to the PLL bandwidth to guarantee system stability under a weak grid. How to optimize the parameters is still unclear. In view of this, this article further summarizes and reviews the existing achievements of single-phase SOGI-PLL, and points out the problems to be solved and the development direction to improve the SOGI-PLL under more complex and non-ideal grid conditions.

Modelling and Transient Synchronization Stability Analysis for PLL-Based Renewable Energy Generator Considering Sequential Switching Schemes

The synchronization characteristics of phase-locked loop (PLL) based renewable energy generators (REG) are considerably sensitive to the grid condition and the inner sequential switching actions of their control system, especially suffered from grid faults. In this article, the general output characteristics of REG systems are investigated considering the nonlinear behaviour of PLL. In addition, general sequential switching control schemes for the entire grid fault process are introduced. Then, to physically determine and theoretically analyze the transient synchronization stability of REG systems, the synchronization model of a REG system for different fault stages is built and presented in the form of rotor swing equations, which are similar to those of a synchronous generator (SG). The proposed model was able to deduce the characteristics of virtual torque, virtual inertia, and virtual damping coefficient of the REG system, and identify the coupling relationship between the angular frequency/magnitude states of the terminal voltage of the REG system during the synchronization process. Thus, the synchronization stability criteria were proposed based on those of the SG, in which the transient instability phenomenon and mechanism for different fault stages is physically explained by the deduced equal area criteria. Finally, the analysis was verified by simulations and experiments.

Applying the Taguchi Method for Investigating the Phase-Locked Loop Dynamics Affected by Hybrid Storage System Parameters

Storage systems play an important role in performance of micro-grids. Storage systems may decrease fluctuations caused by periodic and unpredictable nature of distributed generation resource. Some micro-grids are connected to the network via a grid-interface converter. The phase-locked loop (PLL) is a commonly technique for the grid synchronization of network-connected converters. Various parameters affect the stability of PLL (including the network-side and microgrid-side parameters). The effect of the micro-grid-side parameters on the stability of the PLL has not been studied so far. In this paper, the stability of PLL influenced by microgrid-side parameters has been evaluated after a detailed analytical modeling of micro-grid components (including the production power fluctuations, energy storage system, microgrid-side loads, controller parameters etc.). This paper proposes two new stability analysis criteria for PLL affected by micro-grid and hybrid storage system parameters. Using proposed criteria for stability of PLL, optimized rate of micro-grid and hybrid storage system parameters are obtained using statistical methods (Taguchi approach). Finally, behavior of PLL affected by hybrid storage system is investigated. The simulation results and eigenvalues analysis confirm the theoretical analysis and proposed criteria.

Analysis of Phase-Locked Loop Low-Frequency Stability in Three-Phase Grid-Connected Power Converters Considering Impedance Interactions

Synchronous reference frame (SRF) phase-locked loop (PLL) is a critical component for the control and grid synchronization of three-phase grid-connected power converters. The PLL behaviors, especially its low-frequency dynamics, influenced by different grid and load impedances as well as operation mode have not been investigated yet, which may not be captured by conventional linear PLL models. In this paper, we propose a state-feedback quasi-static SRF-PLL model, which can identify and quantify the inherent frequency self-synchronization mechanism in the converter control system. This self-synchronization effect is essentially due to the converter interactions with grid impedance and power flow directions. The low-frequency nonlinear behaviors of the PLL under different grid impedance conditions are then analyzed, which forms the framework of evaluating the impacts of the large penetration level of distributed generation units, weak grid, microgrid, and large reactive power consumption in terms of the frequency stability of PLL. Specifically, the PLL behavior of the converter system under islanded condition is investigated to explain the PLL instability issues and the related islanding-detection methods in early publications and industry reports.

Adaptive control of PLL using neural network

Abstract This paper proposes a method for increasing capture range of a phase-locked loop (PLL). The behavior of PLL in the initial condition is nonlinear. This nonlinearity phenomenon is caused by phase detector (PD). A method using neural network as controller in PLL is proposed for overcoming this problem. In the proposed method, the reference frequency and frequency of VCO converted to voltage by FTV. Frequency tracking is achieved by neural network. The circuit has been fabricated in a standard 0.13 μm CMOS process. Simulation results show a tracking range of 110 MHz, and a capture range of 90 MHz while operating from a 2 V supply with maximum 2.18 mW power consumption.

Analysis of jitter in phase-locked loops

Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first- and second-order. Theoretical analysis is supported by results obtained using mixed-signal behavior simulation.

Performance of phase-locked loop frequency synthesiser using accumulative phase detector

The performance of phase-locked loop circuits is critically dependent on the phase detector design. The author considers the use of an unusual phase detector that is capable of linear operation over an arbitrarily wide operating range. This provides the benefits of analytically predictable transient behaviour, without cycle slipping, under all likely conditions of operation and with the prospect of improved acquisition speed. The behaviour of phase-locked loops incorporating such a design is demonstrated analytically and subsequently confirmed by experimental results.

Chaos in phase-locked loops

The chaotic behaviour of phase-locked loops (PLL) in tracking a received signal whose frequency is varying linearly with time is studied. This system is described by a third-order nonlinear autonomous equation. The Lyapunov exponents and dimension of the system are calculated to confirm the chaotic phenomenon. Numerical results indicate that the parameter ranges where the chaos could occur are realistic in the typical designs.

Digital Phase-Locked Loop Behavior with Clock and Sampler Quantization

This paper deals with the analysis of digital phase-locked loop (DPLL) models that take into account the discrete nature of the analog-to-digital converter (ADC) and the numerical controlled oscillator (NCO). The models are general enough to allow for different kinds of noise distributions and nonuniform qnantization. Weak assumptions on the nature of the loop parameters reduce the models to finite Markov chain problems. It is shown that the resulting probability transition matrices are lumpable, which translates into convenient Computational savings. In this manner, an exact statistical analysis is possible not only for first-order but also for second-order loops. Numerical results give evidence that for appropriate ADC and NCO characteristics, few quantization levels are needed to match the performance of models that ignore qnantization. However, when the values of these characteristics are not proper, a substantial change in performance can occur. This change in the loop behavior cannot be analyzed or predicted by those models that neglect the quantization effects. It is also found that the use of a nonlinear ADC improves the loop behavior when the noise density distribution is heavy-tailed, e.g., atmospheric noise.

Acquisition behaviour of phase-locked loops employing an imbalanced phase detector in the absence of noise

The ‘balanced mixer’, when used as a phase detector in phase-locked loops, can exhibit varying characteristics, which depend mainly on the ratio of the input signal level and the imbalance factor. In the paper, the effect of using imbalanced mixers in phase-locked loops on the acquisition behaviour of the loop has been investigated. A formula that describes the acquisition boundaries of the loop has been obtained for the general case, when an imbalanced detector of various characteristics is used. This formula compares very well with well known special cases of detector characteristics, such as those given by sinusoidal or triangular relationships.

Comments on "Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference"

Comments on "Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference"

Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference

The behavior of a second-order phase-locked loop (PLL) in the presence of an interfering signal has been analyzed by different authors with different results. The discrepancy is attributed to the presence or absence of an automatic gain controlled amplifier preceeding the PLL. Simulation results verify that the presence of the automatic gain controlled amplifier reduces the tendency of the PLL to break lock from the desired signal in favor of the interfering signal

Phase-Locked Loop Behavior near Threshold

The phase-locked loop behavior is analyzed following the quasilinearization Booton's method. When the loop is locked on an unmodulated input signal with a static phase error, the phase detector nonlinearity produces an interaction between the static phase error and the voltage-controlled-oscillator (VCO) noise phase fluctuations. Formulas allowing one to compute the static phase error increase and the VCO phase variance increase are derived. When the input signal is phase modulated, there is an interaction between the static phase error, the VCO noise phase fluctuations, and the input signal phase modulation. Formulas are obtained that allow one to compute the loop loss of performances (static phase error increase and VCO phase variance increase) and the coherent phase demodulator output signal-to-noise ratio decrease. Finally, a slight modification to Booton's procedure is proposed, leading to results in better agreement with experimental data.

Corrections to "Phase-Locked Loop Behavior near Threshold"

Corrections to "Phase-Locked Loop Behavior near Threshold"

Phase locked loop: An application in temperature telemetry and a method for its evaluation

Application of a phase locked loop (PLL) in the front end circuitry of a temperature telemetry system is outlined. Some of the features inherent in PLL operation are discussed which make them more powerful than a Schmitt trigger circuit, and applicable to analysis of many types of frequency signals. The general mode of PLL operation is outlined and a simple method developed whereby PLL behavior can be optimized.

Phase-plane analysis of phase-locked loops with rapidly varying phase error

Nonlinear behaviour of phase-locked loops with rapidly varying phase error is examined by using computer phase-plane analysis. The phase variation is modeled by a sinusoidal function. Threshold loop parameters are presented for both sinusoidal and sawtooth phase comparators.

Transient Behavior of a Phase-Locked Loop in the Presence of Noise

Transient behavior of the first-order phase-locked loop in the presence of noise is investigated. Numerical integration is used to obtain solutions for the Fokker-Planck equation which represents loop dynamics, Results illustrate quantitative behavior of the time-varying probability density function of phase error when the input is a constant frequency sinusoid in the presence of additive white Gaussian noise. Several selected values of signal-to-noise ratio (SNR) are considered.