Phase Crystallization Of Amorphous Silicon Research Articles

Solid phase crystallization of amorphous silicon at the two-dimensional limit.

The epitaxy of silicene-on-Ag(111) renewed considerable interest in silicon (Si) when scaled down to the two-dimensional (2D) limit. This remains one of the most explored growth cases in the emerging 2D material fashion beyond graphene. However, out of a strict silicene framework, other allotropic forms of Si still deserve attention owing to technological purposes. Here, we present 2D Solid Phase Crystallization (SPC) of Si starting from an amorphous-Si on Ag(111) in atomic coverage to gain a crystalline-Si layer by post-growth annealing below 450 °C, namely Complementary Metal Oxide Semiconductor (CMOS) Back-End-of-Line (BEOL) thermal budget limit. Moreover, considering the benefit of the 2D-SPC scheme, we managed to write crystalline-Si pixels on the amorphous-Si matrix. Our in situ and ex situ analyses show that an in-plane interface or a lateral heterojunction between amorphous and crystalline-Si is formed. This amorphous-to-crystalline phase transformation suggests that 2D silicon may stem from an epitaxially grown layer and thermal self-organization/assembling.

Kinetics of solid phase crystallization of amorphous silicon analyzed by Raman spectroscopy

Solid phase crystallization (SPC) of amorphous silicon films grown by low pressure chemical vapor deposition was conducted using a tube furnace in nitrogen ambient at temperatures ranging from 560 °C to 1000 °C. The transformed crystalline fraction shows typical sigmoidal curves as a function of annealing time using Raman analysis adopted in this work. Arrhenius plot of the measured incubation time does not fit to the straight line since SPC kinetics has strong temperature dependence and since the heating rate is slow when using a conventional heating method. The grain size decreases as the annealing temperature increases. It, however, is not sensitive to the annealing temperature beyond 800 °C, since SPC kinetics is complete during the period of heating-up according to Raman spectroscopy. It was observed that doping of impurity atoms affect the crystallization kinetics.

Laser annealing of thin film polycrystalline silicon solar cell

Performances of thin film polycrystalline silicon solar cell grown on glass substrate, using solid phase crystallization of amorphous silicon can be limited by low dopant activation and high density of defects. Here, we investigate line shaped laser induced thermal annealing to passivate some of these defects in the sub-melt regime. Effect of laser power and scan speed on the open circuit voltage of the polysilicon solar cells is reported. The processing temperature was measured by thermal imaging camera. Enhancement of the open circuit voltage as high as 210% is achieved using this method. The results are discussed.

Defect annealing processes for polycrystalline silicon thin-film solar cells

► Defect annealing processes were applied to polycrystalline silicon thin films. ► Conventional rapid thermal annealing was compared to novel annealing processes using a laser system and a zone-melting recrystallization setup. ► The open circuit voltages could be enhanced from below 170 mV up to 482 mV. ► Increase in Sun's- V OC values with decrease in FWHM of the TO Raman phonon of crystalline silicon. ► Solar cells were fabricated for I – V -measurements: Best solar cell efficiency of 6.7%. A variety of defect healing methods was analyzed for optimization of polycrystalline silicon (poly-Si) thin-film solar cells on glass. The films were fabricated by solid phase crystallization of amorphous silicon deposited either by plasma enhanced chemical vapor deposition (PECVD) or by electron-beam evaporation (EBE). Three different rapid thermal processing (RTP) set-ups were compared: A conventional rapid thermal annealing oven, a dual wavelength laser annealing system and a movable two sided halogen lamp oven. The two latter processes utilize focused energy input for reducing the thermal load introduced into the glass substrates and thus lead to less deformation and impurity diffusion. Analysis of the structural and electrical properties of the poly-Si thin films was performed by Suns- V OC measurements and Raman spectroscopy. 1 cm 2 cells were prepared for a selection of samples and characterized by I – V -measurements. The poly-Si material quality could be extremely enhanced, resulting in increase of the open circuit voltages from about 100 mV (EBE) and 170 mV (PECVD) in the untreated case up to 480 mV after processing.

Reduced Reflection in polycrystalline silicon thin films through ion implantation induced surface textures and deposition of silver nanostructures

ABSTRACTThis work investigates a novel method to enhance light trapping within polycrystalline silicon (poly-Si) thin films for photovoltaic applications. The method combines the use of hydrogen ion implantation for creation of surface textures in poly-Si thin films and the deposition of silver nanostructures on the textured surface. Poly-Si thin films were prepared by solid phase crystallization of amorphous silicon (a-Si) layer deposited on a SiO2/Si substrate. The a-Si was annealed at various temperatures 600 -1050 °C for 48 hours to grow grains of different size in p-Si, as confirmed by x-ray diffraction (XRD) measurements. These samples were then implanted with 20-keV hydrogen ions to a dose of 1017/cm2, and some with an additional implant with 90-keV argon ions to a dose 5×1015 /cm2. Following implantation, these samples were annealed in an Ar ambient at different temperatures. Surface blistering effects were observed using an optical microscope. Optical specular reflection measurements in the spectral range 400-1100 nm indicated that the reflectance of the samples with higher blistering had decreased remarkably from 40% to 10%. Lastly, the poly-Si samples with various textures were deposited with silver thin film followed by annealing in nitrogen ambient for forming Ag nanostructures on textured poly-Si surfaces. Scanning Electron Microscope (SEM) was used to image the surface structures. The formation of Ag nanoparticles on the poly-Si surface, with textures created by implantation followed by low-temperature annealing (e.g., 400 °C), can significantly reduce light reflection as opposed to the case with Ag nanoparticles formed on an un-textured, poly-Si surface.

Crystallization of thin-film Si monitored in real time by in-situ spectroscopic techniques

We have developed optical techniques for real-time, in-situ monitoring of crystallization and epitaxial growth of silicon. Real-time spectroscopic ellipsometry is used for evaluating epitaxial growth during hot-wire CVD (HWCVD) reveals the thickness at which epitaxy fails and amorphous cones start to nucleate. To distinguish the various processes related to solid phase crystallization of amorphous silicon, we employ, instead, an in-situ real-time reflectance spectroscopy technique, which is simpler and less expensive. Here, we demonstrate the sensitivity of reflectivity spectroscopy to key changes in materials properties. By analyzing reflectance in strongly absorbing UV and transparent IR spectral regions, we distinguish and study the: (1) crystallization mode (random crystallization or solid-phase epitaxy); (2) nucleation location (uniformly in bulk, near film-substrate interface, or film surface); and (3) hydrogen effusion prior to crystallization.

Grain Size Control by Means of Solid Phase Crystallization of Amorphous Silicon

AbstractThe grain size of thermally crystallized a-Si films is controlled by the nucleation, rN, and growth, rG, rates according to the standard Avrami's theory. Despite this evidence, most papers devoted to improve the crystallized grain size analyze their results with a qualitative reference to this theory. In this paper, we will show that one can identify the standard set of rN and rG values for a-Si and that experiments show that deviations from this standard values always result in a smaller grain size. It is also shown that one cannot expect any substantial improvement with non-conventional heat treatments. Finally, it is argued that a larger grain size is expected from a-Si films containing, in their as-grown state, a controlled density of embedded nanocrystals.

Solid phase crystallization of amorphous silicon on glass by thin film heater for thin film transistor (TFT) application

A new process for solid phase crystallization (SPC) of amorphous silicon (a-Si) using thin film heater is reported. With this localized Ti silicide thin film heater, we successfully crystallized 500 Å-thick a-Si in a few minutes without any thermal deformation of glass substrate. The size of crystallized silicon grain was abnormally big (30–40 μm). Polycrystalline thin film transistors (TFT) fabricated using this unique thin film heater showed better mobility than those of conventional ones by furnace annealing.

The model of solid phase crystallization of amorphous silicon under elastic stress

Solid phase crystallization of an amorphous silicon (a-Si) film stressed by a Si3N4 cap was studied by laser Raman spectroscopy. The a-Si films were deposited on Si3N4 (50 nm)/Si(100) substrate by rf sputtering. The stress in an a-Si film was controlled by thickness of a Si3N4 cap layer. The Si3N4 films were also deposited by rf sputtering. It was observed that the crystallization was affected by the stress in a-Si films introduced by the Si3N4 cap layer. The study suggests that the elastic stress increases with crystallization due to the smaller elastic modulus of a-Si with respect to crystalline silicon (c-Si). It is most reasonable to think that the elastic stress does not relax and that the elastic energy increased with crystallization because the elastic modulus of a-Si is smaller than that of c-Si. The experimental data was fitted by this model and the difference of the enthalpy ΔHac between a-Si and c-Si which is the latent heat of crystallization obtained by the fitting showed good coincidence with the previously reported value.

Electrical and noise properties of thin-film transistors on very thin excimer laser annealed polycrystalline silicon films

Thin-film transistors, fabricated on polycrystalline silicon films prepared by combined solid phase crystallization of amorphous silicon and excimer laser annealing processes, have been investigated by electrical and low frequency noise measurements in relation to the active layer thickness and the laser energy density. The device performance is improved with increasing the laser energy density until a critical value where the film is completely melted. By decreasing the active layer thickness from 50 to 25 nm, although the subthreshold characteristics are improved, the electron mobility and the threshold voltage are degraded. The noise data indicate that the degradation is related to electron trapping in both gate and substrate oxide interface traps.

Low temperature solid phase crystallization of amorphous silicon at 380 °C

Amorphous silicon (a-Si) was crystallized by metal induced crystallization (MIC) in an electric field. A 2 nm Ni layer on a-Si was used for the crystallization. The MIC temperature can be reduced to 380 °C in an electric field of 360 V/cm. The Ni-MIC poly-Si has a crystalline volume fraction of 92% with an average grain size of ∼150 nm. The fact that the crystallization temperature can be reduced appears to be due to the enhancement of NiSi2 migration through a-Si in an electric field.

Polycrystalline silicon thin films formed by metal-induced solid phase crystallization of amorphous silicon

Metal-induced solid phase crystallization (MISPC) was performed on plasma-enhanced chemical vapor deposited a-Si:H films which were deposited at substrate temperatures between 100 and 320 °C on bare or SiNx-coated Corning code 7059 glass substrates. The nickel or palladium layers used in the MISPC were thermally evaporated on the a-Si:H film surfaces to thicknesses of 5, 10, or 15 Å. We then examined the MISPC kinetics and its dependence on the precursor a-Si:H deposition temperature, the substrate coating, and the metal layer thickness. For the metals used in this study, it is found that the crystallization time and the microstructure and size of grains in the MISPC polycrystallization silicon (poly-Si) films are independent of the precursor a-Si:H deposition temperature, the metal layer thickness, and the substrate coating; however they are dependent on the metal type. It is argued that the formation of silicides and the solubility of metal in silicon, during the annealing, play important roles in enhancing crystallization. It is also found out that the diffusion of metal impurities into silicon from the metal layer used in the MISPC is detrimental to the electrical properties of the forming poly-Si and to the characteristics of thin film transistors fabricated in the poly-Si.

Polycrystalline silicon thin-film transistors: A continuous evolving technology

Polysilicon thin-film transistors (TFTs) are of great interest for their application in large area microelectronics and in particular for active matrix liquid crystal displays. This is owing to the improved performances of polysilicon TFTs that allow the fabrication of active matrix devices with integrated driving circuitry. The progressive improvement of this technology has been related to the optimization of the polysilicon active layer, first deposited by LPCVD, then obtained by solid phase crystallization of amorphous silicon and, more recently, by excimer laser crystallization of amorphous silicon. For circuit application there is a strong demand for high performances, high stability and low noise devices. Some specific aspects of the electrical characteristics of the polysilicon TFTs and related to their circuit application are also discussed, including the electrical instabilities induced by hot-carrier effects, the anomalous drain current increase occurring at high source-drain voltages (called “kink” effect) and the low-frequency noise performances.

Optical in situ monitoring of solid phase crystallization of amorphous silicon

Solid phase crystallization of amorphous silicon proceeds via random nucleation and growth of crystalline nuclei. We demonstrate a simple technique that allows to extract characteristic energy barriers governing the crystallization process. Low pressure chemical vapor deposition from disilane serves to deposit amorphous Si films at 450°C, which are then crystallized at temperatures around 600°C. Monitoring the time-dependent optical transmission of the crystallizing Si film allows for the calculation of the energetic barriers of the crystallization process without knowing the optical constants of the films under investigation.

Comparison Between Rapid Thermal and Furnace Annealing for A-Si Solid Phase Crystallization

AbstractRapid thermal annealing and furnace annealing for the solid phase crystallization of amorphous silicon thin films deposited using PECVD from argon diluted silane have been compared. Results reveal that the crystallization time, the growth time, and the transient time are temperature activated, and that the resulting polycrystalline silicon grain size is inversely proportional to the annealing temperature, for both furnace annealing and rapid thermal annealing. In addition, rapid thermal annealing was found to result in a lower transient time, a lower growth time, a lower crystallization time, and smaller grain sizes than furnace annealing, for a given annealing temperature. Interestingly, the transient time, growth time, and crystallization time activation energies are much lower for rapid thermal annealing, compared to furnace annealing.We propose two models to explain the observed differences between rapid thermal annealing and furnace annealing.

Phenomenological theory of explosive solid phase crystallization of amorphous silicon

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