Phase Compensation Circuit Research Articles

All-passive multiple-place optical phase noise cancellation

We report on the realization of delivering coherent optical frequency to multiple places based on passive phase noise cancellation over a bus topology fiber network. This technique mitigates any active servo controller on the main fiber link and at arbitrary access places as opposed to the conventional technique, in which an active phase compensation circuit has to be adopted to stabilize the main fiber link. Although the residual fiber phase noise power spectral density in the proposed technique turns out to be a factor of seven higher than that of in the conventional multiple-access technique when the access place is close to the end of the fiber link, it could largely suppress the phase noise introduced by the servo bumps, improve the response speed and phase recovery time, and minimize hardware overhead in systems with many stations and connections without the need for active servo circuits including phase discriminators and active compensators. The proposed technique could considerably simplify future efforts to make precise optical frequency signals available to many users, as required by some large-scale science experiments.

A compact Doherty power amplifier for massive multi‐input multi‐output applications

AbstractA Doherty power amplifier composed of GaAs IPDs (Lange coupler and Doherty combiner) and GaN MMICs (carrier amplifier and peaking amplifier) is presented for 5G massive multi‐input multi‐output (MIMO). No input phase compensation circuit and no output offset lines were used for a compact design and the assembled Doherty power amplifier is as small as 6.6 mm × 3.6 mm with a saturation output power of 46 dBm. The asymmetric Doherty power amplifier exhibits a gain greater than 27.8 dB, PAE greater than 39.8% at average output power of 38 dBm, and ACLR less than −27.7 dBc using a 20 MHz LTE signal with 7.5 dB PAR across 3.6‐3.8 GHz.

Robust Position Sensorless Technique for a PMBLDC Motor

The main objective of this paper is to present a new mechanical sensorless control technique of a permanent magnet brushless dc (PMBLDC) motor, which relies on the speed independent H functions. Two major challenges in the sensorless operation of PMBLDC motor drive are the starting the motor and driving it from a low speed to the rated speed. A speed independent H function is used to decide the commutation instant. Due to speed independence, the commutation instant is predicted even at low speed. The H function depends only on line voltages, which makes the overall system simple and cost effective. The proposed technique does not require any analog filter circuit or any phase compensation circuit. To eliminate the commutation ripple from the line voltages, digital low-pass filters and digital phase compensators are used. This makes the system compact, simple, and cost effective. This cost-effective solution proves perfect for low-cost appliances such as fan, air-conditioner, refrigerator, vacuum cleaner, and other home appliances. The proposed algorithm is implemented on a low-cost DSP (TMS320F28377S) to justify the effectiveness of the proposed sensorless technique for wide speed variation.

A 6-Bit 0.13 μm SiGe BiCMOS Digital Step Attenuator with Low Phase Variation for K-Band Applications

This paper presents the design and measuring of a 6-bit SiGe BiCMOS digital step attenuator, with a maximum attenuation of 31.5 dB, and with 0.5 dB steps (64 states) that have the lowest RMS amplitude error and a low phase variation. To alleviate the large phase variation of the conventional attenuator at a higher frequency, the proposed attenuator utilizes a phase compensation circuit. The phase compensation circuit consists of a 2nd order low pass phase correction network, stacked in parallel to the switched π/T structure of each attenuation module. An attenuator with a phase compensation network shows a root mean square (RMS) amplitude error less than 0.43 dB, and the RMS insertion phase deviation varying from 1.6° to 4.2° over 20–24 GHz. The measured insertion loss is 21.9 dB and the input P1dB is 14.03 dBm at 22 GHz. Our confidence regarding the obtained results stems from a comparison of simulations, carried out using Cadence Virtuoso, and physical measurements using a network analyzer (also presented). The proposed attenuator’s design has a 0.13 μm SiGe BiCMOS process, with an approximate occupied area of 1.92 × 0.4 mm2 including chip pads.

23:1 Bandwidth ratio quasi‐lumped component balun on a multilayer organic substrate

Author(s): Pham, BL; Ta, HH; Pham, AV; Leoni, RE; Leviatan, Y | Abstract: In this study, the authors present the design and development of a novel ultra-wideband coupled-line balun on a multilayer liquid crystal polymer substrate. The balun is designed using a quarter wavelength (λ/4) asymmetric broadside coupled line. The defected ground structure and a lumped phase compensation circuit are developed to achieve wide bandwidth performance for the balun. The balun has a measured bandwidth ratio of 23:1, from 80 to 1860 MHz. Within the operating bandwidth, the experimental results demonstrate that the balun achieves an input return loss of better than 10 dB, an insertion loss of better than 1 dB, an amplitude imbalance of better than ±0.4 dB and a phase imbalance of better than ±10°. The size of the balun is 40.64 mm × 40.64 mm or 0.22 λg × 0.22 λg, where λg is the guided wavelength at the centre frequency of 970 MHz.

Special issue: selected papers from NORCHIP 2014 conference

32nd Norchip Conference was held at Tampere, Finland in October 2014. The Nordic Microelectronics event has been the annual meeting-place of Nordic IC and ASIC designers since 1983, when it was first held in Copenhagen. Already in early 1980s MPW runs were constantly arranged for Nordic research institutes and this helped to educate the designers needed for the 1990s telecommunication boom, for example. Since 1992 Springer (initially Kluwer) has published a special issue containing the best papers of the conference. Now Norchip conference is following the path of ESSCIRC: due to gradually reducing number of attendants, it will change to a combined conference with a bit broader scope. In 2015 the meeting will not be called Norchip anymore, but joined together with SoC conference, it will continue under a name of NORCAS (IEEE Nordic Circuits and Systems Conference). So NORCHIP is signing out, but warmly welcomes NORCAS to continue as a meeting forum of IC and ASIC designer. Interested readers are welcomed to read a short history of the conference at http:// www.norchip.org/NORCHIP_HISTORY.htm and submit their papers to NORCAS (http://www.norcas.org/). The strength of Norchip has always been that it has plenty of presentations showing fabricated and tested circuits. For this special issue I chose eight interesting papers that I’ll introduce now briefly. ‘‘Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs’’ by Muntal et al. presents a highvoltage driver circuit for capacitive micromachined ultrasonic transducers (CMUT). Implementing a large array of transducers for a portable ultrasound scanner forced the designers to minimize the power needed in the level translating circuit and carefully choosing proper type of transistors for the partially high-voltage application. ‘‘A 4 9 128 SPAD array with a 78-ps 512-Channel TDC for time-gated pulsed Raman spectroscopy’’ by Nissinen et al. is another high-voltage application, where pn diodes are biased in avalanche breakdown region to implement very high-gain photo-receivers, where a single photon is sufficient for triggering a timing pulse in a complete long-range, low-power laser radar. ‘‘Integrated 16-Channel Neural Recording and Stimulation Circuit’’ by Kursu et al. shows the implementation of a system for real-time recording of neural signals that may eventually help us to understand what cockroaches really think about human beings or life in general. ‘‘A novel cascading scheme to improve the performance of voltage multiplier circuits’’ by Chouchan et al. is a timely implementation of an RF energy harvester circuit operating at 433 MHz. The active rectifying circuit was modified to give higher efficiency at high input powers. ‘‘A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit’’ by Tired et al. describes a twochip PLL system and preliminary results for controlling the phase of a 80 GHz transmission. It is designed using 1.5 V, 200 GHz SiGe HBT process. ‘‘W-Band Phase Shifter in 28-nm CMOS’’ by Vahdati et al. is another paper related to electrical beam-steering applications. It presents a 4-step controllable, 39 mW, 1-V phase shifter for 80–100 GHz band. & Timo Rahkonen timor@ee.oulu.fi

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with fT = 200 GHz. The PLL is intended to be used for beam steering in an 81---86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals ?115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals ?100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers.

CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application

This paper presents a novel CMOS Doherty power amplifier (PA) with an impedance inverter using a variable balun transformer (VBT) and adaptive bias control of an auxiliary amplifier. Unlike a conventional quarter-wavelength (λ/4) transmission line impedance inverter of a Doherty PA, the proposed VBT impedance inverter can achieve load modulation without any phase delay circuit. As a result, a λ/4 phase compensation circuit at the input path of the auxiliary amplifier can be removed, and the total size of the Doherty PA can be reduced. Additionally, an enhancement of the power efficiency at backed-off power levels can successfully be achieved with an adaptive gate bias in a common gate stage of the auxiliary amplifier. The PA, fabricated with 0.13-μm CMOS technology, achieved a 1-dB compression point (P1 dB) of 31.9 dBm and a power-added efficiency (PAE) at P1 dB of 51%. When the PA is tested with 802.11g WLAN orthogonal frequency division multiplexing (OFDM) signal of 54 Mb/s, a 25-dB error vector magnitude (EVM) compliant output power of 22.8 dBm and a PAE of 30.1% are obtained, respectively.

Design of Bandwidth-Enhanced Doherty Power Amplifiers for Handset Applications

A quarter-wavelength impedance transformer as well as a number of other factors limit the bandwidth (BW) of Doherty power amplifiers (PAs). We utilize the lower Q of a quarter-wave length transformer and propose a phase compensation circuit and an additional offset line to be incorporated into the matching net works for an enhanced BW of the Doherty PA. The quarter-wave length transformer and the final output circuit have the same Q. Input dividing networks are also analyzed for operation of broad BW. The Doherty PA for long term evolution (LTE) applications is integrated into a 1.4 × 1.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die using an InGaP/GaAs hetero junction bipolar transistor (HBT) process. For an LTE signal with a 7.5-dB peak-to-average power ratio (PAPR) and a 10-MHz BW, the PA with a supply voltage of 4.5 V delivers a power-added ef ficiency (PAE) of 36.3% and an adjacent channel leakage ratio (ACLR) of -32 dBc with an average output power of 27.5 dBm at a frequency of 1.85 GHz. Across frequencies from 1.6-2.1 GHz, the PA performs with a PAE of more than 30%, a gain of more than 28 dB and an ACLR of less than -31 dBc at an average output power of 27.5 dBm while satisfying the standard spectrum mask. These figures verify that the proposed bandwidth enhancement techniques are effective for handset Doherty PAs.

Differential pickup circuit design of a kind of Z-axis MEMS quartz gyroscope

The MEMS quartz gyroscope is composed by a tuning fork and the detection circuits. The tuning fork's error noise of a quartz gyroscope will have significant influence on it's performance. The mechanical coupling error noise still existed after design and processed, normally this kind of error noise can be reduced by some other methods such as laser trim, but the capacitor coupling error noise can’t be reduced by these methods. This paper introduces differences between error sources of a kind of z-axis quartz gyroscope and y-axis quartz gyroscope. The capacitor error noise of z-axis quartz gyroscope is larger than that of y-axis quartz gyroscope. According to characteristics of z-axis quartz gyroscope's coupling error noise signal, the differential and phase compensation circuit is designed, which can effectively remove the influence of tuning fork's error noise on the z-axis quartz gyroscope's signal, and can effectively improve the z-axis quartz gyroscope's performance.

Design of Doherty Power Amplifiers for Handset Applications

In this paper, we analyze the power drive of a Doherty power amplifier (PA), and introduce a technique for proper input dividing without a coupler. For the proper Doherty operation, we place a phase compensation circuit at the input of the carrier amplifier. We also propose an output matching of Doherty PA to reduce the number of matching components, and to match the output impedances to enhance efficiency and linearity in consideration of the uneven input drive. The PA circuit is fabricated using a 2-μm InGaP/GaAs heterojunction bipolar transistor process and combined for Doherty operation using merged lumped components. For the IEEE 802.16e m-WiMAX signal, which has a 9.54-dB crest factor and 8.75-MHz bandwidth, the PA has an error vector magnitude of 3% and a power-added efficiency of 40.2% at an output power of 26 dBm.

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7ps over the operating frequency range of 200MHz–1GHz and the power consumption is 4.8mW at 1GHz. The maximum lock time is 20 clock cycles.

An analog compensation method for asymmetric IMD characteristics of power amplifier

The modulation frequency affects the asymmetric intermodulation distortion (IMD) products of a RF power amplifier. This effect reduces IMD cancellation performance of power amplifiers in connection with predistortion linearization. A phase extraction method to determine phase difference between upper and lower third-order IMD products and a phase compensation circuit using an envelope injection technique is proposed. The experimental results demonstrate a significant improvement in the third-order IMD cancellation performance.

Design of a sensorless commutation IC for BLDC motors

This paper presents the design and realization of a sensorless commutation integrated circuit (IC) for brushless DC motors (BLDCMs) by using mixed-mode IC design methodology. The developed IC can generate accurate commutation signals for BLDCMs by using a modified back-EMF sensing scheme instead of using Hall-effect sensors. This IC can be also easily interfaced with a microcontroller or a digital signal processor (DSP) to complete the closed-loop control of a BLDCM. The developed sensorless commutation IC consists of an analog back-EMF processing circuit and a programmable digital commutation control circuit. Since the commutation control is very critical for BLDCM control, the proposed sensorless commutation IC provides a phase compensation circuit to compensate phase error due to low-pass filtering, noise, and nonideal effects of back-EMFs. By using mixed-mode IC design methodology, this IC solution requires less analog compensation circuits compared to other commercially available motor control ICs. Therefore, high maintainability and flexibility can be both achieved. The proposed sensorless commutation IC is integrated in a standard 0.35-/spl mu/m single-poly four-metal CMOS process, and the realization technique of this mixed-mode IC has been given. The proposed control scheme and developed realization techniques provide illustrative engineering procedures for the system-on-a-chip solution for advanced digital motor control. Simulation and experimental results have been carried out in verification of the proposed control scheme.

Stabilization of Voltage Limiter Circuit for High‐Density DRAMs Using Miller Compensation

AbstractThe feasibility is examined of using the Miller phase‐compensation circuit to ensure the stability of the voltage limiter circuit in high‐density CMOS DRAMs. First, analytical expressions are obtained for the condition of stabilization to support the comprehensive circuit design and it is shown that both load capacity and load current affect the stability significantly. Second, by using the analytical expressions, parameters for the voltage limiter and the phase compensation circuit are calculated. By computer simulation and experiment voltage variations within the chip are evaluated when the internal circuit operates and external power supply voltage is changed. Results show that the voltage variation caused by the operation of the internal circuit is within 10 percent, resulting in no problem in practice.The voltage variation caused by the change in the external power supply voltage is 3 percent in the case of low‐frequency noise (tr, tf = 1μs) and is as large as 20 percent in the case of high‐frequency noise (tr, tf = 10 ns) and attention must be paid to the latter case in the circuit design.

Development of advanced generator excitation control regulator (PSVR) for improving voltage stability of a bulk power transmission system

Earlier generator excitation control systems were based on AVR control of generator terminal voltage. This system cannot accommodate reactive power up to the facility limit even when the power system voltage decreases to the limit for stable operation. An attempt was made to develop an advanced excitation control system (PSVR) to achieve higher constant sending end voltage of power stations. The intent was to apply the system to the generator connected to a 500-kV system which contributes most effectively to the voltage stability of a bulk power transmission system. This PSVR produces higher control gains than the AVR, and the following functions were adopted: (1) AVR gain reduction circuit; (2) phase compensation circuit; and (3) damping improvement by enlarging the limiter of the PSS. In addition, various functions were provided, e.g., voltage slope characteristics to balance the reactive power of adjacent generators and PSVR output and terminal voltage limiter to stabilize the generator operation. Before application to a real system, a transient response test was performed by combining the PSVR and a generator simulator to verify the damping improvement and stability of the voltage control.