Stabilization of Voltage Limiter Circuit for High‐Density DRAMs Using Miller Compensation

Abstract

AbstractThe feasibility is examined of using the Miller phase‐compensation circuit to ensure the stability of the voltage limiter circuit in high‐density CMOS DRAMs. First, analytical expressions are obtained for the condition of stabilization to support the comprehensive circuit design and it is shown that both load capacity and load current affect the stability significantly. Second, by using the analytical expressions, parameters for the voltage limiter and the phase compensation circuit are calculated. By computer simulation and experiment voltage variations within the chip are evaluated when the internal circuit operates and external power supply voltage is changed. Results show that the voltage variation caused by the operation of the internal circuit is within 10 percent, resulting in no problem in practice.The voltage variation caused by the change in the external power supply voltage is 3 percent in the case of low‐frequency noise (tr, tf = 1μs) and is as large as 20 percent in the case of high‐frequency noise (tr, tf = 10 ns) and attention must be paid to the latter case in the circuit design.