Hardware Perspective Research Articles

Assessing the quantum-resistant cryptographic agility of routing and switching IT network infrastructure in a large-size financial organization

This paper provides exploratory research by determining the impact of quantum computing threat on modern routing and switching infrastructure components of IT network infrastructure in a large-size financial organization. We determine whether common routing and switching IT network infrastructure, including its hardware and software components, have enough cryptographic agility to accommodate the change of cryptographic algorithms to the ones that do not exhibit vulnerability to quantum computing and to the ones that are compliant with National Security Agency (NSA) Suite B set of protocols. We pinpoint upstream or downstream impacts of a change in the encryption algorithms across various IT network infrastructure components in terms of effort required to accomplish this transition.This study is among the first studies that investigate quantum-resistance cryptographic from the hardware perspectives of routing and switching technologies using diffusion of innovation theory. The study integrates enterprise governance to meet the challenges presented by quantum-computing with a focus on cryptographic agility.We offer an enterprise architecture framework for assessing the dependencies, costs, and benefits of IT infrastructure migration plan to meet the future challenges of quantum-resistant cryptographic. The analysis in this research can be used by IT managers to pre-plan for an upgrade of routing and switching infrastructure, assist in estimating the efforts required to perform these upgrades, and assist in selecting a vendor of routing and switching equipment from the perspective of cryptographic agility. With today's supercomputers, a computational task involved in breaking modern asymmetric cryptographic algorithms would be infeasible due to the required computational complexity. However, with progress in the development of quantum computing technology, firms are facing an increasing risk of potential security threats to existing encrypted data and secured transmission channels as the processing power of quantum computers continue to increase.

Low-Cost and Efficient Hardware Solution for Presentation Attack Detection in Fingerprint Biometrics Using Special Lighting Microscopes

Biometric recognition is already a big player in how we interact with our phones and access control systems. This is a result of its comfort of use, speed, and security. For the case of border control, it eases the task of person identification and black-list checking. Although the performance rates for verification and identification have dropped in the last decades, protection against vulnerabilities is still under heavy development. This paper will focus on the detection of presentation attacks in fingerprint biometrics, i.e., attacks that are performed at the sensor level, and from a hardware perspective. Most research on presentation attacks has been carried out on software techniques due to its lower price as, in general, hardware solutions require additional subsystems. For this paper, two low-cost handheld microscopes with special lighting conditions were used to capture real and fake fingerprints, obtaining a total of 7704 images from 17 subjects. After several analyses of wavelengths and classification, it was concluded that only one of the wavelengths is already enough to obtain a very low error rate compared with other solutions: an attack presentation classification error rate of 1.78% and a bona fide presentation classification error rate (BPCER) of 1.33%, even including non-conformant fingerprints in the database. On a specific wavelength, a BPCER of 0% was achieved (having 1926 samples). Thus, the solution can be low cost and efficient. The evaluation and reporting were done following ISO/IEC 30107-3.

Secure Internet of Things (IoT)-Based Smart-World Critical Infrastructures: Survey, Case Study and Research Opportunities

The widespread adoption of the Internet of Things (IoT) technologies has drastically increased the breadth and depth of attack surfaces in networked systems, providing new mechanisms for the intrusion. In the context of smart-world critical infrastructures and cyber-physical systems, the rapid adoption of the IoT systems and infrastructures without thorough consideration for the risks and vulnerabilities has the potential for catastrophic damage to the privacy, safety, and security of individuals and corporations. While the IoT systems have the potential to increase productivity, accountability, traceability, and efficiency, their potential weaknesses are also more abundant. In this paper, we provide critical consideration of the security of the IoT systems as applied to smart-world critical infrastructures. Particularly, we carry out a detailed assessment of vulnerabilities in IoT-based critical infrastructures from the perspectives of applications, networking, operating systems, software, firmware, and hardware. In addition, we highlight the three key critical infrastructure IoT-based cyber-physical systems, namely the smart transportation, smart manufacturing, and smart grid. Moreover, we provide a broad collection of attack examples upon each of the key applications. Furthermore, we introduce a case study, in which we assess the impacts of potential attacks on critical IoT-based systems, using the smart transportation system as an example. Finally, we provide a set of best practices and address the necessary steps to enact countermeasures for any generic IoT-based critical infrastructure system.

Studies of behaviour of the automatic control system of roadheader cutting heads movement

Boom–type roadheaders are basic machines used in underground mines for drilling roadways, in tunnelling and also for making underground buildings using trenchless methods. The article presents selected results of tests carried out in a semi–industrial scale, on a roadheader R–130, concerning behaviour of an innovative solution of system for automatic control of boom–type roadheader cutting heads’ movements. This important innovation, not known before in mining cutting machines, is the software control of cutting heads angular speed using a frequency converter. The text shows an impact of key values, from a perspective of an assumed control purpose, of programming device (setting system) parameters, achieving reference values for the actuators, on controlled facility behaviour when cutting a layered cement and sand block. The performance of the automatic control system without and with feedback to the setting system concerning an actual speed of cutting heads movement, which is important from the control system hardware perspective, was compared.

Cryptanalysis of Chaos-Based Cryptosystem from the Hardware Perspective

Chaos has been used in cryptography for years and many chaotic cryptographic systems have been proposed. Their securities are often evaluated by conducting conventional statistical tests, however few studies have referred to the security issue of the chaotic hardware cryptographic systems. This paper evaluates the security of the chaotic cryptographic system from a hardware perspective by using the side channel analysis attack. First, a chaotic block cryptosystem is designed and implemented based on an Atmel microcontroller. Then the conventional statistical security tests, including SP 800-22 test, characters frequency test, avalanche test, are used to verify its security performance. In the meantime, the correlation power analysis attack is carried out for the security evaluation. Experimental results demonstrate that even though the chaotic cryptographic system can pass the conventional statistical tests, it still has the probability to be attacked from a hardware perspective using the leaked side channel information such as execution time and power consumption. This paper proposes another way to analyze the security of the chaotic cryptosystem, which can aid designing mechanisms to enhance the security of the hardware cryptosystems in the future.

An Effective Security Requirements Engineering Framework for Cyber-Physical Systems

Context and motivation: Cyber-Physical Systems (CPSs) are gaining priority over other systems. The heterogeneity of these systems increases the importance of security. Both the developer and the requirement analyst must consider details of not only the software, but also the hardware perspective, including sensor and network security. Several models for secure software engineering processes have been proposed, but they are limited to software; therefore, to support the processes of security requirements, we need a security requirements framework for CPSs. Question/Problem: Do existing security requirements frameworks fulfil the needs of CPS security requirements? The answer is no; existing security requirements frameworks fail to accommodate security concerns outside of software boundaries. Little or even no attention has been given to sensor, hardware, network, and third party elements during security requirements engineering in different existing frameworks. Principal Ideas/results: We have proposed, applied, and assessed an incremental security requirements evolution approach, which configures the heterogeneous nature of components and their threats in order to generate a secure system. Contribution: The most significant contribution of this paper is to propose a security requirements engineering framework for CPSs that overcomes the issue of security requirements elicitation for heterogeneous CPS components. The proposed framework supports the elicitation of security requirements while considering sensor, receiver protocol, network channel issues, along with software aspects. Furthermore, the proposed CPS framework has been evaluated through a case study, and the results are shown in this paper. The results would provide great support in this research direction.

A Rogowski Digital Integrator With Comb Filter Signal Processing System

In this paper, a new type of Rogowski digital integrator signal processing system has been developed for the dc test platform which located in the Institute of Plasma Physics. This signal processing system is mainly composed of the dual-coil subtraction structure and the digital signal filtering processing method that comb filter combined with high-pass filter (HPF) and low-pass filter (LPF). Trigger noise comes from the converter; it can be coupled to the integrator through distributive capacitance between dc bus bar and Rogowski coil; it will affect the integrator seriously; for example, the amplifier in integrator will be saturation, and the integrator cannot work, burrs lying in integration result. The dual-coil subtraction structure can attenuate the trigger noise significantly from hardware perspective and is convenient for the integrator to take a high gain without saturation. The comb filter combined with HPF and LPF can attenuate the trigger noise further and smooth the integration result. The experiment indicates that the approach proposed in this paper can reduce the impact of trigger noise on the integrator and improve the measurement accuracy.

Electrical Product Compliance and Safety Engineering [Book Reviews

This book covers issues of electrical product compliance and safety in a simple to understand and well-structured reference book. The authors are experienced and highly regarded product safety experts. This is a reference work that is of importance for anybody in the consumer technology field. The book serves as a one-stop reference for electronics/electrical product designers that can help direct them ensure the product being designed is compliant with international safety and compliance requirements. Thus, costly product redesigns and time-to-market delays are reduced. It is also a reference book for safety engineers. The book contains 16 chapters and a detailed glossary of terms and abbreviations used by the safety engineering community. The contents of this book discuss electrical product safety primarily from a device perspective. Some systems concepts are discussed, but this book provides an overview of how to ensure a product is safe, primarily from a hardware perspective. Software is mentioned, but discussing software safety in detail is beyond the scope of this book.

Demonstration of a carrier frequency offset estimator for 16-/32-QAM coherent receivers: a hardware perspective

We propose and implement a hardware-efficient frequency offset estimator (FOE) optimized for 16- and 32-QAM coherent optical receivers with low hardware cost and high estimation accuracy. The proposed FOE combines a wide-range coarse estimator and a narrow-range highly accurate estimator in a feedforward architecture. We numerically and experimentally investigate the performance of the proposed estimator by using a field-programmable-logic-array (FPGA) based real-time coherent receiver. Compared with other state-of-the-art estimators in literature, the proposed method reduces over 40% of hardware utilizations while maintaining the same level of estimation accuracy in terms of mean-squared-error (MSE) and optical signal-to-noise ratio (OSNR) sensitivity. These results enable the development of next generation DSP circuit capable of supporting high capacity coherent optical communication link with advanced modulation formats.

Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.

Towards miniaturized closed-loop optogenetic stimulation devices

Objective. Electrical brain stimulation provides therapeutic benefits for patients with drug-resistant neurological disorders. It, however, has restricted access to cell-type selectivity which limits its treatment effectiveness. Optogenetics, in contrast, enables precise targeting of a specific cell type which can address the issue with electrical brain stimulation. It, nonetheless, disregards real-time brain responses in delivering optimized stimulation to target cells. Closed-loop optogenetics, on the other hand, senses the difference between normal and abnormal states of the brain, and modulates stimulation parameters to achieve the desired stimulation outcome. Current review articles on closed-loop optogenetics have focused on its theoretical aspects and potential benefits. A review of the recent progress in miniaturized closed-loop optogenetic stimulation devices is thus needed. Approach. This paper presents a comprehensive study on the existing miniaturized closed-loop optogenetic stimulation devices and their internal components. Main results. Hardware components of closed-loop optogenetic stimulation devices including electrode, light-guiding mechanism, optical source, neural recorder, and optical stimulator are discussed. Next, software modules of closed-loop optogenetic stimulation devices including feature extraction, classification, control, and stimulation parameter modulation are described. Then, the existing devices are categorized into open-loop and closed-loop groups, and the combined operation of their neural recorder, optical stimulator, and control approach is discussed. Finally, the challenges in the design and implementation of closed-loop optogenetic stimulation devices are presented, suggestions on how to tackle these challenges are given, and future directions for closed-loop optogenetics are stated. Significance. A generic architecture for closed-loop optogenetic stimulation devices involving both hardware and software perspectives is devised. A comprehensive investigation into the most current miniaturized and tetherless closed-loop optogenetic stimulation devices is given. A detailed comparison of the closed-loop optogenetic stimulation devices is presented.

Impacts of Memory Address Mapping Scheme on Reducing DRAM Self-Refresh Power for Mobile Computing Devices

With the growth of the Internet of Things (IoT), increasingly, more computing tasks are implemented on power-sensitive mobile devices, causing a bottleneck on energy consumption. Most mobile devices consume considerable power in the standby mode, during which the capacitive DRAM cells’ self-refresh power, which is used to preserve data integrity, accounts for a large part. To address this issue, strategies from both hardware and software perspectives have been proposed, and yet, the existing hardware methods usually have a high cost. Software strategies mainly focus on the operating system page allocation strategy to maximize resource idleness. The partial array self-refresh technique has been proposed to allow for some of the DRAM cells to retain the self-refresh state while shutting down the others. Using this technique, numerous studies extend the unused DRAM idle time by clustering the applications’ data but do not discuss the impact of the address mapping mechanism on power consumption. However, this impact was proven to be essential in our previous study. In this paper, we attempt to investigate the impacts of different memory mapping schemes on different clustering strategies using a hierarchy-based memory management system (HBMM) and provide insights for selecting the optimal schemes. The experimental results on the Android platform demonstrate that the schemes and strategies are closely correlated, and memory idle time can be prolonged 125 times with their suitable combination. Conversely, the worst scheme may decrease memory idleness by 12% compared with the original system. Furthermore, our studies on a physical platform show that standby power consumption can be saved by 23% when using HBMM combined with the best clustering strategy.

Rejuvenating direct modulation and direct detection for modern optical communications

High-speed transoceanic optical fiber transmission using direct modulation (DM) and direct detection (DD) was one of the most stirring breakthroughs for telecommunication in 1990s, which drove the internet as a global phenomenon. However, the later evolution of optical coherent communications in 2000s gradually took over the long-haul applications, due to its superior optical spectral efficiency. Nowadays, DM–DD systems are dominant mainly in cost- and power-sensitive short-reach applications, because of its natural characteristics—the simplicity. This paper reviews the recent advances of DM–DD transceivers from both hardware and signal processing perspectives. It introduces a variety of modified DM and/or DD systems for 3 application scenarios: very-short-reach interconnect with little fiber channel impact; single or a few spans of fiber transmission up to several hundred km; and distance beyond the 2nd scenario. Besides the DM–DD and multi-dimension DM–DD with polarization diversity, this paper focuses on how to rejuvenate traditional DM and DD technologies in order to bridge the transmission application gap between DM-DD and coherent transceivers, using technologies such as dispersion compensation, signal field recovery from the intensity-only DD receiver, and complex direct modulation with coherent detection. More than 30 years since the birth, DM and DD still hold indispensable roles in modern optical communications.

What drives smartwatch purchase intention? Perspectives from hardware, software, design, and value

Although wearable devices are popular in recent years, the market share of smartwatches is relatively low. The main goal of this research is to investigate the antecedents of the intention to purchase a smartwatch. This research develops a conceptual model and hypotheses based on the theory of reasoned action and perceived values from the perspectives of software, hardware, and aesthetic design. An online questionnaire was developed and distributed on popular websites to collect data, and 260 usable responses are collected from the potential users of the Apple Watch in Taiwan. The thirteen hypotheses were validated by using partial least squares (PLS) techniques. Among the antecedents of purchase intention in the model, the attitude towards using smartwatches was found to have the strongest direct effect. Among the factors of the attitude, design aesthetics have the most significant effect. The results also show that all of the factors about smartwatch attributes directly affected the related perceived values. However, social value and performance/quality value did not affect the intention. The model demonstrated relatively good explanatory power for purchase intention in the context of smartwatches. The proposed model can provide insights to smartwatch vendors to develop their new products and marketing strategies.

Energy-Efficient Resource Utilization for Heterogeneous Embedded Computing Systems

In this paper, the joint optimization problem with energy efficiency and effective resource utilization is investigated for heterogeneous and distributed multi-core embedded systems. The system model is considered to be fully a heterogeneous model, that is, all nodes have different maximum speeds and power consumption levels from the perspective of hardware while they can employ different scheduling strategies from the perspective of applications. Since the concerned problem by nature is a multi-constrained and multi-variable optimization problem in which a closed-form solution cannot be obtained, our aim is to propose a power allocation and load balancing strategy based on Lagrange theory. Furthermore, when the problem cannot be fully solved by Lagrange approach, a data fitting method is employed to obtain core speed first, and then load balancing schedule is solved by Lagrange method. Several numerical examples are given to show the effectiveness of the proposed method and to demonstrate the impact of each factor to the present optimization system. Finally, simulation and practical evaluations show that the theoretical results are consistent with the practical results. To the best of our knowledge, this is the first work that combines load balancing, energy efficiency, hardware heterogeneity and application heterogeneity in heterogeneous and distributed embedded systems.

Long range iris recognition: A survey

The term “iris” refers to the highly textured annular portion of the human eye that is externally visible. An iris recognition system exploits the richness of these textural patterns to distinguish individuals. Iris recognition systems are being used in a number of human recognition applications such as access control, national ID schemes, border control, etc. To capture the rich textural information of the iris pattern regardless of the eye color, traditional iris recognition systems utilize near-infrared (NIR) sensors to acquire images of the iris. This, however, restricts the iris image acquisition distance to close quarters (less than 1 m). Over the last several years, there have been numerous attempts to design and implement iris recognition systems that operate at longer standoff distances ranging from 1 m to 60 m. Such long range iris acquisition and recognition systems can provide high user convenience and improved throughput. This paper reviews the state-of-the-art design and implementation of iris-recognition-at-a-distance (IAAD) systems. In this regard, the design of such a system from both the image acquisition (hardware) and image processing (algorithms) perspectives are presented. The major contributions of this paper include: (1) discussing the significance and applications of IAAD systems in the context of human recognition, (2) providing a review of existing IAAD systems, (3) presenting a complete solution to the design problem of an IAAD system, from both hardware and algorithmic perspectives, (4) discussing the use of additional ocular information, along with iris, for improving IAAD accuracy, and (5) discussing the current research challenges and providing recommendations for future research in IAAD.

Cyber Security Threats to IoT Applications and Service Domains

We are currently living in the post-PC era where smartphones and other wireless handheld devices are changing our environment, making it more interactive, adaptive and informative. Termed as Internet of Things (IoT) evolving into Internet of Everything, the new ecosystem combines wireless sensor networks, cloud computing, analytical data, interactive technologies, as well as smart devices, to provision solutions in which the objects are embedded with network connectivity and an identifier to enhance object-to-object interactions. IoT innovation is advancing and provides diverse smart solutions or applications. From e-transport to e-health; smart living to e-manufacturing and many other e-solutions. In this environment, the rising trend of cyber attacks on systems infrastructure coupled with the system inherent vulnerabilities presents a source of concern not only to the vendors, but also to the consumer. These security concerns need to be addressed in order to ensure user confidence so as to promote wide acceptance and reap the potentials of IoT. From the perspectives of firmware, hardware and software infrastructure setups, this paper looks at some of the major IoT application and service domains, and analyze the cybersecurity challenges which are likely to drive IoT research in the near future.

Discussion on the System Structure and Capacity Building of Highway Emergency Management in China

The highway development in China is in the ascendant, but its operation time is shorter than the operation time of western developed countries, especially for highway emergency management, which is lagging no matter in practice or in experience. The most important reason should be attributed to lack of a set of effective emergency management system. The system is a combination of hardware and software, namely it is the embodiment of system framework and ability. The paper points out “four-supporting mechanism” from the perspective of hardware and comes up with “six-capacity mechanism” from the perspective of software.

Locality based warp scheduling in GPGPUs

As the need for high performance computing continues to grow, it becomes more and more urgent to design a massive multi-core processor with high throughput and efficiency. However, when the number of cores keeps increasing, the capacity of on-chip memory is always insufficient. In a multi-core processor such as GPGPU (General Purpose Graphic Processor Unit), dozens or hundreds of SMs (Stream Multi-processor) coordinate to gain high throughput with several MB on-chip memory. Furthermore, in one SM, thousands of threads are organized as thread blocks to process instructions in a SIMT (Single Instruction Multiple Threads) manner. As all the threads share the same on-chip memory, the mismatch between large core number and small on-chip memory capacity can easily impair the performance due to excessive thread contention for cache resource.An efficient thread scheduling method is a promising way to alleviate the problems and to boost performance. From the hardware perspective, the instructions are executed by warps which are made up by a fixed number of threads. So we propose a novel warp scheduling scheme to maintain data locality and to relieve cache pollution and thrashing issues. First, to make full use of time locality, we put the disordered warps into a supervised warp queue and issue the warps from oldest to youngest. To utilize space locality and to hide computation unit stalls, we put forward a new insertion method called LPI (Locality Protected Insertion) to reorder warps in the supervised warp queue to better hide long-latency warps with short-latency warps such as ALU operations and on-chip accesses. Over a wide variety of applications, the new scheduling method gains at most 10.1% and an average of 2.2% improvements over the baseline loose round-robin scheduling.

Heterogeneous computing

Hardware and software perspectives.