Persistent Memory Research Articles

Dopamine D1R-neuron cacna1c deficiency: a new model of extinction therapy-resistant post-traumatic stress.

Post-traumatic stress disorder (PTSD) is characterized by persistent fear memory of remote traumatic events, mental re-experiencing of the trauma, long-term cognitive deficits, and PTSD-associated hippocampal dysfunction. Extinction-based therapeutic approaches acutely reduce fear. However, many patients eventually relapse to the original conditioned fear response. Thus, understanding the underlying molecular mechanisms of this condition is critical to developing new treatments for patients. Mutations in the neuropsychiatric risk gene CACNA1C, which encodes the Cav1.2 isoform of the L-type calcium channel, have been implicated in both PTSD and highly comorbid neuropsychiatric conditions, such as anxiety and depression. Here, we report that male mice with global heterozygous loss of cacna1c exhibit exacerbated contextual fear that persists at remote time points (up to 180 days after shock), despite successful acute extinction training, reminiscent of PTSD patients. Because dopamine has been implicated in contextual fear memory, and Cav1.2 is a downstream target of dopamine D1-receptor (D1R) signaling, we next generated mice with specific deletion of cacna1c from D1R-expressing neurons (D1-cacna1cKO mice). Notably, D1-cacna1cKO mice also show the same exaggerated remote contextual fear, as well as persistently elevated anxiety-like behavior and impaired spatial memory at remote time points, reminiscent of chronic anxiety in treatment-resistant PTSD. We also show that D1-cacna1cKO mice exhibit elevated death of young hippocampal neurons, and that treatment with the neuroprotective agent P7C3-A20 eradicates persistent remote fear. Augmenting survival of young hippocampal neurons may thus provide an effective therapeutic approach for promoting durable remission of PTSD, particularly in patients with CACNA1C mutations or other genetic aberrations that impair calcium signaling or disrupt the survival of young hippocampal neurons.

Optimizing synchronization mechanism for block-based file systems using persistent memory

Existing block-based file systems employ buffer caching mechanism to improve performance, which may result in data loss in the case of power failure or system crash. To avoid data loss, the file systems provide synchronization operations for applications to synchronously write the dirty data in DRAM cache back to the slow block devices. However, the synchronization operations can severely degrade the performance of the file system since violating the intention of buffer caching mechanism. In this paper, we propose to relieve the overhead of synchronization operations while ensuring data reliability by utilizing a small Persistent Memory. The proposed Persistent Memory assisted Write-back (PMW) mechanism includes a dedicated Copy-on-Write mechanism to guarantee data consistency and a write-back mechanism across PM and the block devices. We implement the proposed PMW in Linux kernel based on Ext4. The experimental results show that PMW can achieve about 2.2× and 1.6× performance improvement over the original Ext4 and AFCM, the state-of-the-art PM-based synchronization mechanism, on the TPCC workload, respectively.

Dash

Byte-addressable persistent memory (PM) brings hash tables the potential of low latency, cheap persistence and instant recovery. The recent advent of Intel Optane DC Persistent Memory Modules (DCPMM) further accelerates this trend. Many new hash table designs have been proposed, but most of them were based on emulation and perform sub-optimally on real PM. They were also piece-wise and partial solutions that side-step many important properties, in particular good scalability, high load factor and instant recovery. We present Dash, a holistic approach to building dynamic and scalable hash tables on real PM hardware with all the aforementioned properties. Based on Dash, we adapted two popular dynamic hashing schemes (extendible hashing and linear hashing). On a 24-core machine with Intel Optane DCPMM, we show that compared to state-of-the-art, Dash-enabled hash tables can achieve up to ∼3.9× higher performance with up to over 90% load factor and an instant recovery time of 57ms regardless of data size.

Magnetoresistive Random Access Memory: Present and Future

Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

Novelty Exposition Facilitates Memory Extinction By Dopaminergic Mechanisms

Memory extinction has been considered an interesting strategy for attenuating responsiveness to the original fear memory, and has been widely used on clinic to treat fear‐related disorders. However, exposure therapy tend to require a long and slow process of treatment and generally produce transient fear reduction that is often bound to the context in which the therapy was administered. Here we investigate the effects of novelty exposure on memory extinction. 50 male Wistar rats were divided in five groups: (i) control; (ii) novelty exposure; (iii) familiar context exposure; (iv) dopamine; and, (v) dopamine + familiar. All animals were trained in Inhibitory Avoidance (IA) and 24h after submitted to extinction training carried out in three sessions 90 min apart. 24 hours after the last extinction session, the animals were submitted to the retention test, which also made 3, 7, 14 and 21 days after the extinction sessions. Thirty minutes before the first extinction training session, rats from the group (ii) were exposed for 5 min to a novelty (a novel environment). Additional control groups were exposed to a familiar environment. The animals from dopamine groups received an intrahippocampal infusion of dopamine (1 μg/μL, 1 μL per side). During the IA training, all the animals presented similar step‐down latency when compared to each other (P > 0.05). In the 24h retention test the step‐down latency of the group (ii) was significantly lower than the one of control group (i) (P<0.01), indicating that novelty promoted memory extinction. On the other hand, the group (iii) (Familiar OF) present similar step‐down latency than group (i) (P>0.05) and differences from group (ii) (P<0.01), indicating that the exposure to a familiar environment does not promote memory extinction. The group (iv) presented significantly lower latencies than control (i) and familiar (iii) groups (P<0.01), indicating that dopamine promoted memory extinction. On the other hand, the group (iv) present similar step‐down latency than group (ii) (novelty) (P>0.05), indicating that the dopamine mimics novelty effects on memory extinction. Regarding the memory persistence, we observed that the group (ii) presented step‐down latencies significantly lower than control group (i) throughout the 21 days (P<0.01 in all tests). The group (iv) also presented step‐down latencies significantly lower than control group (i) throughout the 21 days (P<0.05 in all tests). Therefore, the exposure to a novelty, as well as, the infusion of dopamine on CA1 region of the hippocampus, promoted persistent memory extinction. In the present work we confirmed that novelty exposure can facilitated the aversive memory extinction and demonstrated that the novelty effects can persist along the time. Finally, we show that the novelty effects on extinction are mimicked by dopamine infusion on CA1 region of hippocampus, reinforcing the importance of hippocampal dopamine on novelty effects.Support or Funding InformationThis work was supported by research grants and fellowships from Fundação de Amparo à Pesquisa do Rio Grande do Sul (FAPERGS), CAPES, Federal University of Pampa, and the National Council of Research of Brazil (CNPq).A. Training, extinctions, and 24h test step‐down latencies on IA. B. Training, extinctions, and 3, 7, 14 and 21 days test step‐down latencies on IA. In each session, different letters represent significant differences between the groups (P < 0.05; Kruskall‐Wallis followed by Dunn’s post‐hoc). * P < 0.05 in comparison to training (Wilcoxon test, training vs. test).Figure 1

Single machine graph analytics on massive datasets using Intel optane DC persistent memory

Intel Optane DC Persistent Memory (Optane PMM) is a new kind of byte-addressable memory with higher density and lower cost than DRAM. This enables the design of affordable systems that support up to 6TB of randomly accessible memory. In this paper, we present key runtime and algorithmic principles to consider when performing graph analytics on extreme-scale graphs on Optane PMM and highlight principles that can apply to graph analytics on all large-memory platforms. To demonstrate the importance of these principles, we evaluate four existing shared-memory graph frameworks and one out-of-core graph framework on large real-world graphs using a machine with 6TB of Optane PMM. Our results show that frameworks using the runtime and algorithmic principles advocated in this paper (i) perform significantly better than the others and (ii) are competitive with graph analytics frameworks running on production clusters.

A Consistency Mechanism for Distributed Persistent Memory File System

A Consistency Mechanism for Distributed Persistent Memory File System

Multigranularity Space Management Scheme for Accelerating the Write Performance of In-Memory File Systems

Emerging nonvolatile memory (NVM) techniques, such as phase change memory (PCM), spin-transfer torque magnetic random access memory (STT-MRAM), and resistive random-access memory, are promising for high-performance data process by reserving data in the memory hierarchy. Many persistent memory file systems are tailored to achieve high performance by exploring the advanced features of the NVM and the hardware memory management unit (MMU) in the CPU. However, with the efficient storage device and the hardware acceleration, the write routines in persistent memory file systems pose considerable overhead since repeatedly allocating free blocks and constructing the file mapping structure are time consuming. In this article, we propose a new multigranularity space management scheme (MSMS) to accelerate the write performance. The MSMS employs multigranularity structured blocks whose mapping structure is proactively constructed to slash the overhead of allocating new space and constructing the file mapping structure. Moreover, we present efficiently dedicated space allocation algorithms for different write modes. For append write, we present a file-sizeand buffer-sizebased allocation (FBA) algorithm to efficiently allocate the appropriate blocks. And for copy-on-write, we present an updating data and offset-based allocation algorithm to preferentially allocate structured huge blocks for reducing the overhead of invoking allocation routines. Based on the new design, we have implemented the MSMS for SIMFS in the Linux kernel. Experimental results show that the MSMS significantly reduces the times of invoking allocation routines. The average append write and copy-on-write performance with the MSMS improve by 16.34% and 7.51%, respectively.

A persistent memory advantage is specific to grapheme-colour synaesthesia

For people with synaesthesia ordinary stimuli such as digits or letters induce concurrent experiences such as colours. Synaesthesia is associated with a memory advantage and the aim of this study was to investigate whether this advantage persists across time. We tested recognition memory of four different types of synaesthesia with different inducer-concurrent pairings across two sessions with a one-year retention interval. In the study phase, participants learned three kinds of stimuli (i.e., related to their inducer, related to their concurrent, or synaesthesia-unrelated): music, words and colours. Recognition memory was tested after one hour and after one year. After one hour, grapheme-colour and grapheme-colour-and-sound-colour synaesthetes showed synaesthesia-specific advantages. After one year, only grapheme-colour synaesthetes still showed an advantage. The results imply that a benefit through enhanced colour-processing is particularly strong and that synaesthesia can lead to a long-lasting memory benefit.

Remote memory of drug experiences coexists with cognitive decline and abnormal adult neurogenesis in an animal model of cocaine-altered cognition.

Cocaine addiction is a chronic disorder in which the person loses control over drug use. The past memories of the stimuli associated with the drug are a relevant clinical problem, since they trigger compulsive drug-seeking and drug-taking habits. Furthermore, these persistent drug-related memories seemingly coexist with cognitive decline that predicts worse therapeutic output. Here, we use a new animal model of cocaine-altered cognition that allowed to observe these events in the same individual and study their relationship. Mice were chronically administered cocaine in a conditioned place preference (CPP) apparatus for 14 days, and control mice received saline. After 28 days of cocaine withdrawal, animals were tested for retrieval of remote drug-associated memory as well as for cognitive performance in a battery of tests, including novel object and place recognition and spatial memory. The cocaine-withdrawn mice showed persistent CPP memory while impaired in the cognitive tasks, displaying deficits in reference memory acquisition and working memory. However, the CPP expression was not associated with the defective cognitive performance, indicating that they were concomitant but independent occurrences. After completion of the experiment, adult hippocampal neurogenesis (AHN) was studied as a relevant neurobiological correlate due to its potential role in both learning and drug addiction. Results suggested a preserved basal AHN in the cocaine-withdrawn mice but an aberrant learning-induced regulation of these neurons. This paradigm may be useful to investigate maladaptive cognition in drug addiction as well as related therapies.

A Prompt Report on the Performance of Intel Optane DC Persistent Memory Module

In this prompt report, we present the basic performance evaluation of Intel Optane Data Center Persistent Memory Module (Optane DCPMM), which is the first commercially-available, byte-addressable non-volatile memory modules released in April 2019. Since at the moment of writing only a few reports on its performance were published, this letter is intended to complement other performance studies. Through experiments using our own measurement tools, we obtained that the latency of random read-only access was approximately 374 ns. That of random writeback-involving access was 391 ns. The bandwidths of read-only and writeback-involving access for interleaved memory modules were approximately 38 GB/s and 3 GB/s, respectively.

Task Errors Drive Memories That Improve Sensorimotor Adaptation.

Traditional views of sensorimotor adaptation (i.e., adaptation of movements to perturbed sensory feedback) emphasize the role of automatic, implicit correction of sensory prediction errors. However, latent memories formed during sensorimotor adaptation, manifest as improved relearning (e.g., savings), have recently been attributed to strategic corrections of task errors (failures to achieve task goals). To dissociate contributions of task errors and sensory prediction errors to latent sensorimotor memories, we perturbed target locations to remove or enforce task errors during learning and/or test, with male/female human participants. Adaptation improved after learning in all conditions where participants were permitted to correct task errors, and did not improve whenever we prevented correction of task errors. Thus, previous correction of task errors was both necessary and sufficient to improve adaptation. In contrast, a history of sensory prediction errors was neither sufficient nor obligatory for improved adaptation. Limiting movement preparation time showed that the latent memories driven by learning to correct task errors take at least two forms: a time-consuming but flexible component, and a rapidly expressible, inflexible component. The results provide strong support for the idea that movement corrections driven by a failure to successfully achieve movement goals underpin motor memories that manifest as savings. Such persistent memories are not exclusively mediated by time-consuming strategic processes but also comprise a rapidly expressible but inflexible component. The distinct characteristics of these putative processes suggest dissociable underlying mechanisms, and imply that identification of the neural basis for adaptation and savings will require methods that allow such dissociations.SIGNIFICANCE STATEMENT Latent motor memories formed during sensorimotor adaptation manifest as improved adaptation when sensorimotor perturbations are reencountered. Conflicting theories suggest that this "savings" is underpinned by different mechanisms, including a memory of successful actions, a memory of errors, or an aiming strategy to correct task errors. Here we show that learning to correct task errors is sufficient to show improved subsequent adaptation with respect to naive performance, even when tested in the absence of task errors. In contrast, a history of sensory prediction errors is neither sufficient nor obligatory for improved adaptation. Finally, we show that latent sensorimotor memories driven by task errors comprise at least two distinct components: a time-consuming, flexible component, and a rapidly expressible, inflexible component.

A pure hardware-driven scheduler for enhancing bank-level parallelism in a persistent memory controller

Researchers are attempting to exploit the non-volatile nature of Persistent Memory (PM) in various applications. To utilize persistence, many solutions enforce strict, sequential write orderings that are propagated through the cache hierarchy, inevitably resulting in extra write requests. Other solutions introduce persistence logging operations to ensure transactional consistency, which also introduces extra writes. To rationally schedule these write requests, current work classifies the sources of write requests into subtypes at the software level based on the characteristics of the application, subsequently transferring the classified requests as hint messages to the memory controller level for guiding scheduling. However, categorizing diverse applications requires incompatible modifications to software and can degrade both the performance and fairness of the results with respect to low bank-level parallelism and low row-buffer locality. To address these problems, we bypass software intervention and propose PHD-scheduler, a Pure Hardware-Driven scheduler for enhancing bank-level parallelism in PM controller. PHD-scheduler is composed of three main ideas: (1) PHD-scheduler moves the classification into the PM’s controller level rather than intervening in the compatibility of the software, (2) it introduces a dynamic computing mechanism to ensure bank access from centralization to distribution, and (3) it maximizes row buffer locality by reshuffling memory requests with three novel criteria to achieve an appropriate batch scheduling. The experimental results show that PHD-scheduler achieves an average bank-level parallelism improvement of 11.8%. Moreover, performance and fairness are improved by 4.2% and 3.3%, respectively.

Pattern analysis based data management method and memory-disk integrated system for high performance computing

This research proposes a memory-disk integrated system (MDIS) with pattern analysis based data management method. The proposed system consists of a pattern adaptive prefetcher with DRAM-based dual buffers and a PCM-based persistent memory structure. The PCM-based persistent memory module is exploited as conventional main memory and storage layers simultaneously. In this system, to compensate the PCMs unfavorable characteristics, a pattern analysis based prefetching method by using dual DRAM buffers with a small amount of space are designed as a sort of caching layer. The proposed pattern analysis based data management method monitors the miss rate to determine the prefetch policy, e.g., when and what to prefetch. These schemes enable flexible adaptation to the application execution characteristics showing unpredictable and inconsistent workload patterns. In order to evaluate our system, we implemented a trace-driven simulator system and launched the YCSB on Redis, Apache Storm, Apache Spark, and OpenStack Swift. The experimental result shows that the MDIS with a pattern adaptive prefetcher can reduce the total access time by 13.9% compared to the conventional scheme and thus the overall performance of the memory-disk integrated system improves.

Importin-α2 mediates brain development, learning and memory consolidation in Drosophila

Neuronal development and memory consolidation are conserved processes that rely on nuclear-cytoplasmic transport of signaling molecules to regulate gene activity and initiate cascades of downstream cellular events. Surprisingly, few reports address and validate this widely accepted perspective. Here we show that Importin-α2 (Imp-α2), a soluble nuclear transporter that shuttles cargoes between the cytoplasm and nucleus, is vital for brain development, learning and persistent memory in Drosophila melanogaster. Mutations in importin-α2 (imp-α2, known as Pendulin or Pen and homologous with human KPNA2) are alleles of mushroom body miniature B (mbmB), a gene known to regulate aspects of brain development and influence adult behavior in flies. Mushroom bodies (MBs), paired associative centers in the brain, are smaller than normal due to defective proliferation of specific intrinsic Kenyon cell (KC) neurons in mbmB mutants. Extant KCs projecting to the MB β-lobe terminate abnormally on the contralateral side of the brain. mbmB adults have impaired olfactory learning but normal memory decay in most respects, except that protein synthesis-dependent long-term memory (LTM) is abolished. This observation supports an alternative mechanism of persistent memory in which mutually exclusive protein-synthesis-dependent and -independent forms rely on opposing cellular mechanisms or circuits. We propose a testable model of Imp-α2 and nuclear transport roles in brain development and conditioned behavior. Based on our molecular characterization, we suggest that mbmB is hereafter referred to as imp-α2mbmB.

Compatible byte-addressable direct I/O for peripheral memory devices in Linux

Memory devices can be used as storage systems to provide a lower latency that can be achieved by disk and flash storage. However, traditional buffered input/output (I/O) and direct I/O are not optimized for memory-based storages. Traditional buffered I/O includes a redundant memory copy with a disk cache. Traditional direct I/O does not support byte addressing. Memory-mapped direct I/O, which optimizes file operations for byte-addressable persistent memory and appears to the CPU as a main memory. However, it has an interface that is not always compatible with existing applications. In addition, it cannot be used for peripheral memory devices (e.g., networked memory devices and hardware RAM drives) that are not interfaced with the memory bus. This paper presents a new Linux I/O layer, byte direct I/O (BDIO), that can process byte-addressable direct I/O using the standard application programming interface. It requires no modification of existing application programs and can be used not only for the memory but also for the peripheral memory devices that are not addressable by a memory management unit. The proposed BDIO layer allows file systems and device drivers to easily support BDIO. The new I/O achieved 18% to 102% performance improvements in the evaluation experiments conducted with online transaction processing, file server, and desktop virtualization storage.

Embedded Software Optimization for Computation - Intensive Applications

Optimization metrics for compiled code are not always measured in execution clock cycles on the target architecture. Modern cellular telephone or wireless devices, which may download executables over a wireless network connection or backhaul infrastructure, it is often advantageous for the compiler to reduce the size of the compiled code that must be downloaded to the wireless device. By reducing the size of the code, savings are achieved in terms of bandwidth required for each wireless point of download. These are metrics correlated to the dynamic run-time behaviour of not only the compiled code on the target processor, but also the underlying memory system, caches, DRAM, and buses, etc. Despite new generation of embedded systems are getting innovative and computationally powerful with upcoming embedded processors, the market demands more computational-intensive embedded software to be developed on embedded systems. It is very essential to implement efficient embedded software to meet the market demand of embedded systems. These embedded systems are special-purpose computing systems and built to perform very specific embedded applications. And, these embedded applications mainly use three key resources of embedded systems: (1) CPU (2) Run-time memory (3) Persistent memory i.e. NAND/NOR flash memory. This paper summarizes several effective embedded software optimization techniques to optimize CPU usage, Run-time memory, and Persistent memory.

Unexpected Performance of Intel® Optane DC Persistent Memory

We evaluated Intel® OptaneTM DC Persistent Memory and found that Intel's persistent memory is highly sensitive to data locality, size, and access patterns, which becomes clearer by optimizing both virtual memory page size and data layout for locality. Using the Polybench high-performance computing benchmark suite and controlling for mapped page size, we evaluate persistent meemory (PMEM) performance relative to DRAM. In particular, the Linux PMEM support maps preferentially maps persistent memory in large pages while always mapping DRAM to small pages. We observed using large pages for PMEM and small pages for DRAM can create a 5x difference in performance, dwarfing other effects discussed in the literature. We found PMEM performance comparable to DRAM performance for the majority of tests when controlled for page size and optimized for data locality.

Reliability of Hybrid Supercapacitor for Persistent Memory Application

Supercapacitor technology is able to bridge the application gap between chemical batteries and conventional capacitors. Supercapacitors possess a higher energy density than capacitors and a higher power density than electrochemical batteries. The quick charge/discharge ability and long cycle life makes them reliable and applicable where power bursts are required. In efforts to avoid data loss in critical computer applications, such as defense-related, banking, healthcare, etc., persistent memory was created. Persistent memory utilizes backup power from a battery to retain data in Dynamic Random-Access Memory (DRAM) long enough for the data to be transferred to the non-volatile flash in case of a power interruption. To identify failure modes, different reliability tests were performed on the Backup Power Module (BPM): Temperature, Humidity, Bias test, the shelf life test, the cycling test, and the accelerated aging test. From these reliability tests, it was observed that when there is variation in potential across individual cells in the pack, it will accelerate the aging of all the cells connected in series. Also, the cycling test gave an indication of reducing charge/discharge time when cycles were extended beyond the predefined cycle test count. An experimental design is suggested for future work that varies temperatures and voltages, with the response variable being the ability of a supercapacitor to hold charge in a prolonged cycling test. As a result of these reliability assays, it was determined that a major reliability concern was traced to a manufacturing process and a suggestion for the improving a manufacturing step is made.

METHODS OF USING MICROSOFT WINDOWS FAMILY OPERATING SYSTEMS ON EXTERNAL SYSTEM DRIVE

Computer’s operating system in generally installed on its internal SSD (HDD). When user boot computer, the BIOS loads the boot loader from the internal SSD and the boot loader boots the installed operating system. A boot loader is a computer program that loads an operating system or some other system software for the computer after completion of the power-on self-tests. A boot loader is loaded into main memory from persistent memory. On modern general purpose computers, the boot up process can take tens of seconds, or even minutes, and typically involves performing a power-on self-test, locating and initializing peripheral devices, and then finding, loading and starting an operating system. Booting is complete when the normal, operative, runtime environment is attained. I have Implemented a few methods of using Microsoft Windows family operating systems on external system drive. Keywords : System drive, HDD, SSD, microSD card, operating system, installation files, WIM-file, DISM, Diskpart, BCDboot, Microsoft Windows.