Permeable Base Transistor Research Articles

P -type metal-base transistor

In this work we present data from a novel p-type metal-base transistor with common-base gain α∼1, fabricated at ambient temperature and pressure by electrodepositing sequentially on a p-type Si collector, a Co base and a Cu2O emitter. The high gain and the dependence of potential between emitter and base (VEB) on the potential between collector and base (VCB) when the emitter current (IE) is held constant both suggest that the device functions as a natural permeable base transistor for very thin metal bases.

Hybrid magnetic transistor

We report the development of a hybrid semiconductor–metal–semiconductor permeable-base transistor in vertical architecture. This transistor has a p-type silicon collector, a thin tin layer as base and a magnetoresistive conjugated polymer, poly(9,9-dioctyl-1,4-fluorenylenevinylene), as emitter material. The transistor transport characteristics are dependent on the applied magnetic field and the base transport factor for positive charge carriers is nearly ideal, independently of the magnetic field in the investigated range.

Copper phthalocyanine based hybrid p-type permeable-base transistor in vertical architecture

We demonstrate the production of copper phthalocyanine (CuPc) based p-type hybrid permeable-base transistors, which operate at low voltages having high common-base current gains. These transistors are prepared by evaporating a thin metal layer (Ag or Al) that acts as base on top of a Si substrate that acts as collector. In the sequence CuPc and Au are thermally sublimated to produce the emitter, constituting a quite simple device production procedure with the additional advantage of allowing higher integration due to its vertical architecture.

High current density tris(8-hydroxyquinoline) aluminum-based hybrid transistor in vertical architecture

We report the construction of hybrid permeable-base transistors, in vertical architecture, using tris(8-hydroxyquinoline) aluminum as emitter, a thin gold layer as base, and n-type silicon as collector. These transistors present high common-base current gain, can be operated at low driving voltages, and allow high current density.

Hybrid Permeable‐Base Transistors Based on an Indenofluorene Derivative

Hybrid transistor highs! Hybrid permeable-base transistors are demonstrated (schematic circuit in Figure), which are based on an indenofluorene derivative (structure shown) and which operate by positive-charge-carrier transport. When the base/collector junction is reverse biased, the base transport factor of these devices saturates at nearly 100 %. They can be operated at current densities of the order of 1 mA mm−2.

Theoretical investigation of GaN permeable base transistors for microwave power applications

An electrical and thermal study of submicron GaN multi-finger permeable base transistors (PBTs) is presented. Carrier transport in the intrinsic finger is studied with drift-diffusion and energy balance models, validated against ensemble Monte Carlo simulation; device performances are optimized through an aggressive geometrical scaling. Non-isothermal analysis of the complete multi-finger structure demonstrates the need for a mobility model whose temperature dependence is not confined to low-field parameters. The potential of GaN PBTs for microwave power applications is finally investigated by evaluating the relevant figures of merit.

Resonant Tunneling Permeable Base Transistors With High Transconductance

A GaAs-based resonant tunneling permeable base transistor has been developed and evaluated at room temperature. The transistor is fabricated by overgrowing a tungsten gate placed next to an AlGaAs-GaAs-InGaAs resonant tunneling heterostructure. By changing the gate voltage, the effective conducting area of the tunnel diode can be modulated and the collector-emitter current thus controlled. Peak currents above 300 mA/mm and a maximum transconductance of 270 mS/mm have been obtained.

Highly functional tunnelling devices integrated in 3D

AbstractWe present a new technology for integrating tunnelling devices in three dimensions. These devices are fabricated by the combination of the growth of semiconductor heterostructures with the controlled introduction of metallic elements into an epitaxial layer by an overgrowth technique. First, we use a new type of tunnelling transistor, namely a resonant‐tunnelling permeable base transistor. A simple model based on a piece‐wise linear approximation is used in Cadence to describe the current–voltage characteristics of the transistor. This model is further introduced into a small signal equivalent circuit in order to optimize the performance of the device. In addition to the tunnelling structure below the grating, these transistors may be integrated in 3D by the introduction of another tunnelling structure directly over the metal grating. In the integrated device structure, the gate acts simultaneously on both tunnelling structures and the obtained characteristics are the result of the interplay between the two tunnelling structures and the gate. An equivalent circuit model is developed and we show how this interaction influences the current–voltage characteristics. The gate may be used to adjust the peak voltage of certain peaks in a controlled fashion, which creates a highly functional tunnelling device. These results show the need for a strong interaction between the development of circuit models and processing technology to develop new nano‐electronic devices and circuits. Copyright © 2003 John Wiley & Sons, Ltd.

Design and Fabrication of GaN-based Permeable-Base Transistors

ABSTRACTIn this work, we present the first successful fabrication of an etched grooved GaN-based permeable-base transistor structure. Growth of the device structures was done by Molecular Beam Epitaxy (MBE) on thick HVPE GaN quasi-substrates. The fabrication process took advantage of isolations pads via He implantation and SiN deposition, as well as submicron ICP etching of collector fingers patterned via e-beam lithography. SEM of the finished devices shows smooth etched finger structures and base layer surface with finger sidewall angles of ∼85° for 1:1 and 1:3 finger spacing. Specific contact resistivities of ∼ 3 × 10-6 Ω•cm2 for the ohmic contacts were achieved with Ti/Al/Ni/Au metallization scheme. Preliminary DC testing of the devices show a collector current IC = 140 mA/mm at VCE of 5V and VBE of +0.5V. The maximum transconductance gm is ∼111 mS/mm in the measured collector-emitter bias range. These values are comparable, within the measurement tolerance, to physics-based modeling results.

Realization of a resonant tunneling permeable base transistor with optimized overgrown GaAs interfaces

A resonant tunneling permeable base transistor has been realized experimentally by overgrowing a tungsten grating placed in direct vicinity to a double barrier heterostructure. In this way, we can directly modulate the tunneling current via an embedded gate. Since the quality of the overgrown interface is critical, special attention is paid to this issue, and the effect of different wet etchants prior to overgrowth is studied both by electrical measurements and by the use of an atomic force microscope. A clear dependence of the electrical properties and the crystal quality on the etchants used is found. This is a key result for the realization of our resonant tunneling device.

Physics-based modeling of submicron GaN permeable base transistors

We present the first physics-based nonstationary modeling of a submicron GaN permeable base transistor. Three different transport models are compared: drift-diffusion, energy balance, and ensemble Monte Carlo. Transport parameters and relaxation times used by the carrier transport equations are consistently derived from particle simulation. The current-voltage (I-V) characteristics predicted with the energy balance model are in good agreement with those obtained from direct Monte Carlo device simulation. On the other hand, the drift-diffusion approach appears to be inadequate for the device under study, even if improved high-field mobility models are adopted.

Full band Monte Carlo simulation of electron transport in 6H-SiC

A study of electron transport in 6H-SiC is presented using a full band Monte Carlo simulation model. The Monte Carlo model uses four conduction bands obtained from a full potential band structure calculation based on the local density approximation to the density functional theory. Electron–phonon coupling constants are deduced by fitting the Monte Carlo simulation results to available experimental data for the mobility as a function of temperature. The saturation velocity perpendicular to the c axis is found to be near 2.0×107 cm/s, which is in good agreement with the experimental data available. In the c-axis direction the saturation velocity is much lower (4.5×106 cm/s). There are no direct experimental results available for the saturation velocity in the c-axis direction. A comparison between two-dimensional simulations of a 6H-SiC permeable base transistor, using transport parameters obtained from the Monte Carlo simulations, and experimental I–V characteristics confirms the low value. The physical mechanism behind this result can be explained in terms of the small group velocity in the c-axis direction for reasonable energy levels in combination with band structure effects that limits the energy range that an electron can reach by drift. This effect reduces the mean energy of the carriers for an electric field applied along the c axis and at 1.0 MV/cm the difference in mean energy compared with perpendicular directions is almost one order of magnitude. The mean energy increases with increasing temperature for electric fields in the c-axis direction, while the situation is reversed in perpendicular directions. In general the impact ionization coefficient has the same temperature dependence as the mean energy and this indicates that the impact ionization coefficient for electrons has a positive temperature derivative along the c axis. This may be a serious drawback in the design of high power vertical metal–semiconductor field effect transistors.

Multilayer structures deposited by laser ablation

TiN/Si structures were deposited on Si wafers by pulsed laser deposition technique. The highly conductive TiN films were grown on heated (100) Si substrates by laser ablation of a high purity Ti target in nitrogen reactive atmosphere. Subsequently, the Si layer was deposited by laser ablation of a Si target in vacuum (down to 10 −6 mbar) or in low pressure inert gas. The nitrogen gas pressure and the substrate temperature were found to strongly influence the TiN film structure and orientation. The degree of crystallinity of the Si layer grown on the TiN film was found to depend on Si/TiN collector temperature. Values below 550°C (the threshold of TiN oxidation activation) were used in the experiments. Techniques as X-ray Diffraction (XRD), Fourier Transform Infrared Spectroscopy (FTIR), High Resolution Transmission Electron Microscopy (HRTEM), Scanning Force Microscopy (SFM) have been used to characterize the deposited structures. The TiN/Si structure rectifying properties were tested. The obtained Si/TiN/Si structure could be suitable for the building of Permeable Base Transistor (PBT, vertical MESFET) devices.

AN INVESTIGATION OF THE BLOCKING CHARACTERISTICS OF THE PERMEABLE BASE TRANSISTOR

A numerical study of the blocking characteristics of the Permeable Base Transistor (PBT) is presented. The PBT is regarded as a promising transistor structure for high voltage and high frequency applications. Numerical studies of the PBT were focused on the high frequency figure of merits or the breakdown characteristics of the Schottky gate. A device designed for high frequency and high voltage switching should be optimized for large blocking and fast switching. The trade off between blocking and speed is a complicated matter which depends strongly on the geometry and doping level. In this work we studied the blocking characteristics for a Silicon PBT with regard to the doping level and doping profile, gate thickness and gate to drain distance. A scaling formalism was developed in order to estimate the transistor performance for a wide range of doping levels and geometrical combinations. A design example is presented of a normally off transistor that can block a drain to source voltage of 10 V while the unity current gain frequency f T value for V gs=0.2 V is higher than 7 GHz.

Performance and design of vertical, ballistic, heterostructure field-effect transistors

The influence of ballistic transport and the doping level on the pinch-off voltage in an AlGaAs/GaAs heterostructure permeable base transistor is studied by numerical simulation. It is established that the high velocity of the injected hot electrons prevents a charge build-up in the vertical channel. Therefore, the dependence of the doping on the transconductance is reduced and the doping may, independently, be altered to adjust the pinch-off voltage. These devices are predicted to have an f t above 300 GHz.

Operation of a ballistic heterojunction permeable base transistor

A ballistic heterojunction permeable base transistor (HPBT) is proposed and an analytical and numerical analysis of the device is performed. The new feature of the device structure is an AlGaAs hetero-emitter for injection of hot electrons into a 150-nm-thick GaAs base layer. A tungsten grating is embedded in the base layer and the Schottky depletion around the metal wires controls the vertical current. In this investigation, it is established that the high velocity of the hot electrons will prevent charge accumulation in the base layer. Thereby the dependence of the doping on the transconductance is lower than for the permeable base transistor. The HPBT is expected to have a unity-current gain cut-off frequency above 300 GHz.

Characterization of traps in GaAs/W Schottky diodes by optical and electrical deep-level transient spectroscopy methods

Both the electrical and optical deep-level transient spectroscopy (DLTS) measurement methods were used to investigate the deep traps in GaAs that originate from the impurities included in the Schottky metal on GaAs/W Schottky diodes. Two distinct electron traps (E1 and E2, whose activation energies EA were, respectively, 0.65 and 0.58 eV) were detected by electrical DLTS in samples annealed at 650 °C. The variation of EA and trap density with changes in the Schottky barrier height indicates that the trap E1 can be identified with the EL2 usually observed in the GaAs grown by metalorganic chemical-vapor deposition. In addition, the trap E2 is found to be due to impurities that diffused from the W film into the GaAs layer during annealing. Four hole traps with activation energies of 0.76, 0.55, 0.43, and 0.30 eV were detected by optical DLTS in samples annealed at 650 °C. Comparison of the EA for each hole trap with data previously reported indicates that the first three traps are due to the transition metals Cr, Fe, and Cu, and that the last one is due to a native defect. These metals are confirmed from secondary-ion-mass spectroscopy analysis to be included in the as-deposited W film. Furthermore, these traps are also observed in GaAs permeable base transistors with the buried W gate.

Electrical characterization and physical analysis of epitaxial CoSi2 grown from the Si〈100〉/Ti/Co system

The electrical and structural properties of epitaxial CoSi2 layers grown on Si by solid-state interaction between Ti/Co bimetallic layers and Si〈100〉 substrates have been investigated. The Schottky barrier height (SBH) of the CoSi2–Si contact determined by current–voltage characteristics at room temperature varies between 0.64 and 0.71 eV on the n-type substrates and between 0.47 and 0.43 eV on the p-type substrates. The variation of the SBH is found to be related to the interfacial properties at the CoSi2–Si contact which is in turn determined by the heat treatment used for the CoSi2 formation. The formation of polycrystalline CoSi2 is found to be responsible for the low SBH deviated from 0.71 eV on the n-type substrates and the high SBH deviated from 0.43 eV on the p-type substrates. The formation of a ternary compound, identified as Co16Ti6Si7, within the epitaxial CoSi2 does not seem to affect the SBH on the n-type substrates. A permeable base transistor (PBT) was fabricated using the epitaxial CoSi2 for self-aligned contact metallization. The current–voltage characteristics of the PBTs are presented.

Investigation of hot carrier transport in silicon permeable base transistors

The effects of variations in the source to drain distance have been investigated for several highly doped Permeable Base Transistor (PBT) structures. A detailed study of the hot electron transport in these structures is presented using a 2-D self-consistent full band Monte Carlo (MC) simulation program. The PBT structures considered are the overgrown, etched source and etched drain PBT. Finally we have simulated a structure where both the source and the drain have been etched. All structures have a high doping level in the channel (10/sup 17/ cm/sup -3/) and are operating under a gate biasing far from the threshold voltage. The etched structure shows a larger increase in the unity current gain frequency (f/sub T/) than the overgrown structure as the source to drain distance decreases. By optimizing the source to drain distance of the etched source PBT, the f/sub T/ can be increased by a factor of two. Our Monte Carlo result has been compared with an ordinary drift-diffusion (DD) model and a more advanced energy transport (ET) model. The difference between the MC and DD model is largest for the etched structures, while it is less significant for the overgrown structure. However, all structures considered in this work, long and short channel devices, show a larger dc current level in the MC model. This is related to the large electric field and high carrier temperature near the gate depletion region.

Silicon-wafer fabrication and (potential) applications of direct-bonded silicon

An automatic silicon wafer direct-bonding apparatus, a vacuum stack-bonding apparatus, a parallel polishing machine and a method for measuring a high level of parallelism of silicon wafers are described. These items are essential to wafer preparation and geometrical quality control for direct-bonding applications. Attention is then turned to silicon direct-bonded to a second compound, which presents a wealth of feasible or potential applications, such as silicon-on-silicon for a permeable-base transistor; silicon-on-insulator, prepared for special silicon integrated circuit applications. In addition, silicon bonded to metal, to interdiffusing solids, to superconductors, diamond, a ferroelectric and to polymers for various (potential) applications is discussed.