Peripheral Component Interconnect Research Articles

Design of Novel Optical Fiber Communication Electronic System and Big Data Prediction Method of Its Loss

For the shortcomings of traditional data communication electronic mode and bus interface, optical fiber communication electronic technology and compact peripheral component interconnect (CPCI) bus interface mode with industry standard are adopted to design a kind of optical fiber communication electronic data transmission mode. The optical fiber communication electronic board based on CPCI bus constitutes a novel optical fiber communication electronic system. In the process of hardware design, the small form-factor pluggable (SFP) transceiver module is used to convert the photoelectric signal and complete the transmission of optical fiber data. Regarding the existence of differential signal in high-speed serial circuit of electronic board, the wiring is reasonably arranged. The hardware test platform of optical fiber communication electronic system is built based on PCI9054 CPCI bus and industrial personal computer (IPC) communication electronics. FPGA with embedded high-speed serial transceiver module is adopted to design the hardware logic function. Binary gray code is used to count. FIFO protocol and Aurora protocol are supported. Protocol IP core is customized to realize the full duplex electronic communication of high-speed data. Considering the loss problem of the system, the grey model GM(1, 1), ARIMA model and Elman neural network are employed as the big data level research scheme, which are combined into the loss prediction model according to a certain proportion. In the experiment, the test of DMA data reading and writing function is designed, and the embedded highspeed transceiver module and optical fiber communication electronic logic function are simulated. The results show that the symbol error rate (SER) is always 0, and the low-pass filtering characteristics of the channel are effectively compensated, which makes the signal quality stabler. Compared with the single big data level research scheme, the combined model has smaller prediction error and higher prediction accuracy.

Experimental Investigation and Control of a Hot-Air Tunnel with Improved Performance and Energy Saving.

The paper is focused on the identification, control design, and experimental verification of a two-input two-output hot-air laboratory apparatus representing a small-scale version of appliances widely used in the industry. A decentralized multivariable controller design is proposed, satisfying control-loop decoupling and measurable disturbance rejection. The proposed inverted or equivalent noninverted decoupling controllers serve for the rejection of cross-interactions in controlled loops, whereas open-loop antidisturbance members satisfy the absolute invariance to the disturbances. Explicit controller-structure design formulae are derived, and their equivalence to other decoupling schemes is proven. Three tuning rules are used to set primary controller parameters, which are further discretized. All the control responses are simulated in the Matlab/Simulink environment. In the experimental part, two data-acquisition, communication, and control interfaces are set up. Namely, a programmable logic controller and a computer equipped with the peripheral component interconnect card commonly used in industrial practice are implemented. A simple supervisory control and data acquisition human–machine interface via the Control Web environment is developed. The laboratory experiments prove better temperature control performance measured by integral criteria by 35.3%, less energy consumption by up to 6%, and control effort of mechanical actuator parts by up to 17.1% for our method compared to the coupled or disturbance-ignoring design in practice. It was also observed that the use of a programmable logic controller gives better performance measures for both temperature and air-flow control.

A Special Peripheral Component Interconnect Express Card for Video Surveillance Systems in Alarm Applications

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

Multichannel gas electron multiplier based soft x-ray field-programmable gate array measurement system for W-Environment in Steady-state Tokamak (WEST): Hardware, installation, and first plasma acquisition.

The work describes a novel approach to the design of a fast, multichannel measurement system for plasma diagnostics [A. Wojenski et al., Fusion Eng. Des. 123, 727 (2016)]. Its main scope is to provide measurements of soft X-ray (SXR) emission during plasma phenomena at the W-Environment in Steady-state Tokamak (WEST), especially for monitoring and tracing tungsten impurities. This paper describes the vertical Gas Electron Multiplier (GEM) camera installed at the WEST [M. Chernyshova et al., J. Instrument. 10, P10022 (2015)]. The designed GEM detector readout board has more than 100 channels, resulting in high-performance requirements for the data acquisition and processing system. The novel system construction approach is that the unit works on the raw signals providing a high quality of the data, especially in the scope of pileup effect analysis. In the case of doubtful results, the source data can be easily reviewed offline. The data selection and transmission are done in Field-Programmable Gate Arrays (FPGAs) on the custom boards with the custom Peripheral Component Interconnect (PCI)-Express Gen2 switch that allows us to register signals from multiple FPGAs and then process the data by complex algorithms [G. Kasprowicz et al., J. Fusion Energy 38, 480 (2019)]. The firmware is replaceable and different working modes can be applied (some under verification): global trigger mode, high-speed data serialization, and extended signal registration. Low level optimized central processing unit software for data readout was also designed [P. Linczuk et al., J. Instrum. 14, C05001 (2019)]. The installation of the system is described due to complex system components' distribution. The first results of the successful acquisition of the plasma at the WEST are discussed. The corresponding SXR energy and topology spectra were computed. Those are the first technical measurements of the system to ensure verification of data quality.

Embedded GPU Implementation for High-Performance Ultrasound Imaging

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

Multi-Channel Data Acquisition Card under New Acquisition and Transmission Architecture of High Frequency Ground Wave Radar

It is known that the data acquisition and processing system plays an important role in radar target detection system. In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing the designed acquisition card based on the PCIe (peripheral component interconnect express) has been designed and is presented in this paper. The Xilinx FPGA (Field-Programmable Gate Array) chip Kintex7-XC7K325T is adopted as a hardware carrier in acquisition card. The hardware’s composition, analog front-end circuit, the DMA (Direct Memory Access) transmission, FPGA structure, ADC (Analog-to-Digital Converter) chip, and performance test of this card are showed and discussed. Currently, the acquisition card has been accomplished and applied in the practical system of HFGWR.

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

IBM z15: Physical design improvements to significantly increase content in the same technology

The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

PurposeThe data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.Design/methodology/approachThis work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.FindingsThis paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.Practical implicationsThe typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.Social implicationsIt can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.Originality/valueCompared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

An Electrical and Ultrasonic Doppler System for Industrial Multiphase Flow Measurement

Accurate measurement of flow parameters of multiphase flow has great significance for safe, economic, and efficient operation of the industrial production process. To simultaneously measure the water holdup and velocity, a combined electrical and ultrasonic Doppler measurement system based on a compact peripheral component interconnect (CPCI) bus is designed. The combined sensor consists of a six-ring conductance sensor, two pairs of capacitance plate sensors, and an ultrasonic Doppler sensor. The measurement system is cored with a field-programmable gate array (FPGA) and consists of a series of functional modules. Through flexible programming and interboard communication, the system can meet different measurement requirements. To meet industrial data transmission standards and increase system extensibility, the demodulated data are transmitted to a host computer through the CPCI bus for further data analysis. Dynamic experiments demonstrated that the multimodal system has stable and preferable performance in water holdup and velocity measurement under all flow patterns. The conductance and capacitance sensor could realize the water holdup measurement with the root-mean-square error (RMSE) of 3.02% and the overall superficial velocity estimation through cross correlation with the RMSE of 0.09 m/s. Besides, the pulse ultrasonic Doppler transducer could measure the overall superficial velocity through the area integration of the velocity profile with the RMSE of 0.08 m/s.

Toward a hardware man-in-the-middle attack on PCIe bus

The growing need for high rate communication of recent embedded systems is leading to the adoption of the PCIe protocol (Peripheral Component Interconnect express) as an internal data bus. This technology is used in some recent smartphones, and will probably be adopted globally in the next few years. The communication between the processor (in the SoC) and its memory through the PCIe bus represents an important source of information for criminal investigations. In this paper, we present a new attack vector on PCIe based on a hardware Man-in-the-Middle. This system allows real-time data analysis, data-replay, and a copy technique inspired by the shadow-copy principle. Through this one, it is possible to locate, duplicate, and replay sensitive data. The main challenge here is to develop an architecture compliant with PCIe protocol constraints, such as response time, frequency, and throughput, in order to be non-detectable to the communication parts. We designed a proof of concept of an emulator based on a computer with PCIe 3.0 bus and a Stratix 5 FPGA with an endpoint PCIe port as a development target.

SmartIO

The large variety of compute-heavy and data-driven applications accelerate the need for a distributed I/O solution that enables cost-effective scaling of resources between networked hosts. For example, in a cluster system, different machines may have various devices available at different times, but moving workloads to remote units over the network is often costly and introduces large overheads compared to accessing local resources. To facilitate I/O disaggregation and device sharing among hosts connected using Peripheral Component Interconnect Express (PCIe) non-transparent bridges, we present SmartIO. NVMes, GPUs, network adapters, or any other standard PCIe device may be borrowed and accessed directly, as if they were local to the remote machines. We provide capabilities beyond existing disaggregation solutions by combining traditional I/O with distributed shared-memory functionality, allowing devices to become part of the same global address space as cluster applications. Software is entirely removed from the data path, and simultaneous sharing of a device among application processes running on remote hosts is enabled. Our experimental results show that I/O devices can be shared with remote hosts, achieving native PCIe performance. Thus, compared to existing device distribution mechanisms, SmartIO provides more efficient, low-cost resource sharing, increasing the overall system performance.

Control and indicating equipment communicating via the peripheral component interconnect express bus

Nowadays, the Intruder Alarm system is commonly used to protect the life, health and the possession of people in big companies. However, these systems have limited options for managing and remote control. This lack is very often criticized by big companies which want to use the Intruder Alarm System with other applications like Access and Attendance control. The aim of this article is to design a Control and Indicating Equipment which can be implemented into commercially made Personal Computer as expansion card. The designed card provides the main function of the Intruder Alarm system which can be further extended by other applications. The system consists of external communication like Universal Serial Bus, Ethernet and General Packet Radio Service interface. Each individual part of the system is driven by a single microcontroller ATmega328P which can handle communication and evaluation of the current state obtained by devices connected to it. The design can offer all alarm and non-alarm visualization of smart control like irrigation, lights control, audio system, etc. The whole design is driven by the proper standardization and the design consists of every schematic which comes with the explanation

An Ultrasonic Transmission/Reflection Tomography System for Industrial Multiphase Flow Imaging

Monitoring multiphase flow process and measuring its parameters have been a research topic that received broad attentions for the past decades. Ultrasonic process tomography (UPT) obtains the distribution of the two-phase flow based on ultrasound propagation in different fluids, making it valuable to the industrial monitoring and measurement. UPT can nonintrusively explore transient hydrodynamics of the multiphase flow, but the reconstruction quality of single modality is always dependent on phase distribution. In this paper, a dual-mode UPT that fuses the attenuation and time-of-flight of ultrasound is presented. To implement this scheme, a digital dual-mode UPT system that works under both the transmission-mode and reflection-mode is designed. A 16-channel ultrasound data acquisition system is proposed, which is flexibly programmable and reconfigurable through an field-programmable gate array (FPGA). The system includes a series of functional modules, and is based on the compact peripheral component interconnect bus for real-time data transmission to meet industrial field requirements. Static experiments show that the system can distinguish the interface of the different inclusions and preferably reconstruct the position and area of the inclusions through fusing the transmission and reflection reconstruction, the relative error and correlation coefficient of the reconstructed images are presented, respectively, which show preferable and stable distinguishability of different inclusions.

A review on bus protocols and conversion/translator between different protocols

A computer consists of different components/modules and different communication protocols are used among them. These protocols are needed to achieve the interoperability between two devices/modules. Different protocols cannot communicate directly, there is a need for conversion. A protocol converters block is needed. These compact protocol converters create low power, low voltage connection as well as smaller chip area, making it easy to add multiple devices or components. This paper give a brief description of some commonly used bus protocols such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Advanced Microcontroller Bus Architecture (AMBA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe) and Ethernet. A review of some protocol converter/translator are done with a view to explore their usability.

Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme

Fully homomorphic encryption (FHE) is a technique that allows computations on encrypted data without the need for decryption and it provides privacy in various applications such as privacy-preserving cloud computing. In this article, we present two hardware architectures optimized for accelerating the encryption and decryption operations of the Brakerski/Fan-Vercauteren (BFV) homomorphic encryption scheme with high-performance polynomial multipliers. For proof of concept, we utilize our architectures in a hardware/software codesign accelerator framework, in which encryption and decryption operations are offloaded to an FPGA device, while the rest of operations in the BFV scheme are executed in software running on an off-the-shelf desktop computer. Specifically, our accelerator framework is optimized to accelerate Simple Encrypted Arithmetic Library (SEAL), developed by the Cryptography Research Group at Microsoft Research. The hardware part of the proposed framework targets the XILINX VIRTEX-7 FPGA device, which communicates with its software part via a peripheral component interconnect express (PCIe) connection. For proof of concept, we implemented our designs targeting 1024-degree polynomials with 8-bit and 32-bit coefficients for plaintext and ciphertext, respectively. The proposed framework achieves almost $12\times $ and $7\times $ latency speedups, including I/O operations for the offloaded encryption and decryption operations, respectively, compared to their pure software implementations.

PCIe Hot-Plug Support Standardization Challenges in ATCA

Throughout the last decade, the Advanced Telecommunications Computing Architecture (ATCA) solidified its position as one of the main switched-based crate standards for advanced Physics instrumentation, offering not only highly performant characteristics in data throughput, channel density or power supply/dissipation capabilities, but also special features for high availability (HA), required for latest and upcoming large-scale endeavours, as is the case of ITER. Hot Swap is one of the main HA features in ATCA, allowing for Boards to be replaced in a crate (Shelf), without powering off the whole system. Platforms using the Peripheral Component Interconnect Express (PCIe) protocol on the Fabric Interface must be complemented, at the software level, with the PCIe Hot Plug native feature, currently not specified for the ATCA form-factor. From a customised Hot Plug support implementation for ATCA Node Boards, the paper presents an implementation extension for Hub Boards, allowing Hot Plug of PCIe switching devices, without causing bus enumeration problems. This paper further addresses the main issues concerning an eventual standardization of PCIe Hot Plug support in ATCA, such as the implementability of Hot Plug Elements and the generation and management of Hot Plug Events, aiming to stimulate the discussion within the PICMG community towards a long overdue standardized solution for Hot Plug in ATCA.

Development of the HL-2M digital pulse analysis system

A digital pulse analysis system is an important diagnostic system in nuclear physics experimental research. In response to the demand for reflecting the particle state in a nuclear physics experiment, we have designed and developed a real-time digital pulse analysis system and applied it to the digital nuclear pulse waveform discrimination of different detectors in the HL-2M tokamak. The system is based on the peripheral component interconnect extensions for instrumentation (PXI) platform, while its software was written in LABVIEW. The key technologies involved in the system implementation include digital pulse analysis technology, digital discrimination technology, pulse height analysis technology, etc. The system has been applied to the plastic scintillator detector at the Neutron Source Lab of the University of Science and Technology of China. And the experimental results indicate that the system can discriminate between neutron (n) particles and gamma (γ) particles well when used to measure the plastic scintillator detector.

The data acquisition and control system for the operation of ASDEX pressure gauge for the measurement of neutral pressure in ADITYA Tokamak

Bayard-Alpert (BA) type hot cathode ionisation gauge is widely used to measure neutral pressure precisely in vacuum system below 10−3 Torr pressure. Neutral pressure measurement in magnetic confinement fusion experiments is quite challenging for standard BA type gauge due to higher pressure limitation and its ionisation is affected by strong magnetic and electrical fields. To overcome the above limitations, a special hot cathode ionisation gauge, named ASDEX Pressure Gauge (APG) system was developed by G. Haas at the Max-Planck-Institute, Germany. The APG system can work in high magnetic field up to 6 T and high temperature plasma environment with broad pressure measurement range from 10−1 to 10−6 mbar with fast response (<10 msec) and good noise immunity.In the present work, we report the design and development of control and data acquisition of ASDEX Pressure Gauge (APG) for ADITYA Tokamak to measure real time neutral pressure during the high temperature plasma. The developed system can achieve synchronous control of gauge controller using General Purpose Interface Bus (GPIB) and data acquisition of ion emission current of gauge head using Peripheral Component Interconnect (PCI) based data acquisition module. Initially, the APG calibration with standard BA type hot cathode ionization gauge had been carried out using the test set-up of low magnetic field and ultrahigh vacuum system with gases like H2, Ar, He. For APG calibration for various pressure ranges of these gases, precise gas feed control system has been developed using controller based hardware and LabVIEW based software. After testing and calibration, the APG was installed on ADITYA tokamak and calibrated under high magnetic field of ADITYA. The developed APG control system is configurable for presenting the gauge parameters before the plasma discharge. During plasma discharge, the analog signal equivalent to neutral pressure is acquired in real-time using simultaneous sampling analog to digital converter (ADC) module. The acquired raw data and processed real time pressure can provide valuable neutral pressure/density information of Tokamak plasma.

Quality Evaluation Electronics for CBM-TOF Super Module

The time-of-flight (TOF) system in the compressed Baryonic matter (CBM) experiment is comprised of super modules and used for charged hadron identification. Each super module contains several multigap resistive plate chambers (MRPCs) for high-precision time measurements. The quality of each super module should be evaluated to ensure that the detectors achieve the targeted performance. In this paper, the quality evaluation electronics for super modules based on the peripheral component interconnect eXtensions for instrumentation platform is proposed. The discriminated MRPC signals are digitized by the time-to-digital converter (TDC). Then, the digitized time data from a super module are aggregated at the TDC readout motherboard and are transmitted to the data readout modules (DRMs) via optical links. Finally, the DRMs relay the digitized data to the data acquisition system through the Gigabit Ethernet ports in parallel. The laboratory test results indicate that the quality evaluation electronics achieve a time resolution better than 20 ps. The initial cosmic ray tests with the MRPC detectors have also been conducted to confirm the performance of the quality evaluation system. Based on the results, the evaluation system can subsequently be used for quality evaluation of the CBM-TOF super module.