Performance Speedup Research Articles

Parallel implementation of Red–Black ordering preconditioners for accelerating GMRES solutions in neutron transport code PANDAS-MOC

The PANDAS-MOC uses preconditioners like ILU(0) and SSOR to accelerate the convergence of the GMRES solution in the Multi-level CMFD solver. However, their sequential nature limits their effectiveness on parallel platforms. This paper investigates the performance of Red–Black preconditioners (RB-SSOR, RB-RSOR, RB-ILU) in accelerating the solutions of MG-GMRES and CG-GMRES in the PANDAS-MOC. It uses various benchmark reactors, including TWIGL-2D, C5G7-2D, C5G7-3D, and their corresponding subplane models (TWIGL-2D(5S), C5G7-2D(5S), C5G7-3D(5S)), with relaxed convergence criteria (10−3). The results show that all preconditioners significantly reduce the required number of iterations to converge the GMRES solutions. The paper also explores the strong scaling and hybrid MPI/OpenMP speedup performance of Red–Black preconditioners using the C5G7-3D(5S) problem. Preconditioners present similar sublinear speedup trends across tests for MG-GMRES and CG-GMRES respectively, but the speedup results in CG-GMRES are more than twice as high as those in MG-GMRES. RB-RSOR has an optimal efficiency of 0.6967 at (4,8), while RB-SOR and RB-ILU have their optimal efficiencies of 0.6855 and 0.7275 at (32,1) when executing 32 total threads (= MPI processors × OpenMP threads).

POETS: An Event-driven Approach to Dissipative Particle Dynamics

HPC clusters have become ever more expensive, both in terms of capital cost and energy consumption; some estimates suggest that competitive installations at the end of the next decade will require their own power station. One way around this looming problem is to design bespoke computing engines, but while the performance benefits are good, the design costs are huge and cannot easily be amortized. Partially Ordered Event Triggered System (POETS)—the focus of this article—seeks to exploit a middle way: The architecture is tuned to a specific algorithmic pattern but, within that constraint, is fully programmable. POETS software is quasi-imperative: The user defines a set of sequential event handlers, defines the topology of a (typically large) concurrent ensemble of these, and lets them interact. The “solution” may be exfiltrated from the emergent behaviour of the ensemble. In this article, we describe (briefly) the architecture, and an example computational chemistry application, dissipative particle dynamics (DPD). The DPD algorithm is traditionally implemented using parallel computational techniques, but we re-cast it as a concurrent compute problem that is then ideally suited to POETS. Our prototype system is realised on a cluster of 48 FPGAs providing 50K concurrent hardware threads, and we report performance speedups of over two orders of magnitude better than a single thread baseline comparator and scaling behaviour that is almost constant. The results are validated against a “conventional” implementation.

Parallel processing of E-Atheer algorithm using pthread paradigm

The development in the field of computer technology, and the increase in the growth rate of database, alongside the extraction of certain data from a huge pool of database involve intricate and complex processes. The processes comprise text mining, pattern recognition, retrieval of information and text processing. Thus, the need for enhancing the performance of string matching algorithms is required, which is considered as one of the challenges to the researchers. Consequently, one of the resolution to address this problem is the parallelization for exact string matching algorithms. In this study, we implemented the parallel exact string matching algorithm termed as E-Atheer with multi-core processing utilizing Pthread (POSIX) for the reduction of time consumption. The Pitch, XML, Protein, and DNA database types are utilized to test the impact of the proposed parallel algorithm. The parallelization algorithm obtained positive results in the parallel execution time, and a more superior expediting capabilities, in comparison to the sequential result. The Pitch database indicated optimal results in parallel execution time, and when utilizing long and short pattern lengths. The DNA database indicated optimal speedup performance when utilizing short and long pattern length, meanwhile the XML and Protein on the other hand indicated the worst results.

GANBISS: a new GPU accelerated N-body code for binary star systems

We present a GPU accelerated N-body integrator using the Bulirsch–Stoer method, called GANBISS (GPU accelerated n-body code for binary star systems). It is designed to simulate the dynamical evolution of planetesimal disks in binary star systems which contain some thousand disk objects. However, it can also be used for studies of non-interacting massless bodies where up to 50 million objects can be studied in a simulation. GANBISS shows the energy and angular momentum conservation behavior of non-symplectic integration methods. The code is written in CUDA C and can be run on NVIDIA GPUs of compute capability of at least 3.5. A comparison of GPU and CPU computations indicates a speed-up of the GPU performance of up to 100 times—depending on the number of disk objects.

PHY: A performance-driven hybrid communication compression method for distributed training

Distributed training is needed to shorten the training time of deep neural networks. However, the communication overhead often hurts performance efficiency, especially in a distributed computing environment with limited network bandwidth. Hence, gradient compression techniques have been proposed to reduce communication time. But, compression also has the risk of causing lower model accuracy and longer training time due to compression loss and compression time. As a result, compression may not consistently achieve desired results, and there are limited discussions on when and which compression should be used. To address this problem, we propose a performance-driven hybrid compression solution. We make three main contributions. (1) We describe a hybrid compression strategy that chooses the compression method for individual model gradients. (2) We build an offline performance estimator and an online loss monitor to ensure the compression decision can minimize training time without sacrificing mode accuracy. (3) Our implementation can be imported to existing deep learning frameworks and applicable to a wide range of compression methods. Up to 3.6x training performance speedup was observed compared to other state-of-the-art methods.

FLAME GPU 2: A framework for flexible and performant agent based simulation on GPUs

AbstractAgent based modelling (ABM) offers a powerful abstraction for scientific study in a broad range of domains. The use of agent based simulators encourages good software engineering design such as separation of concerns, that is, the uncoupling of the model description from its implementation detail. A major limitation in current approaches to ABM simulation is that of the trade off between simulator flexibility and performance. It is common that highly optimised simulations, such as those which target graphics processing units (GPU) hardware, are implemented as standalone software. This work presents a software framework (FLAME GPU 2) which balances flexibility with performance for general purpose ABM. Methods for ensuring high computational efficacy are demonstrated by, minimising data movement, and ensuring high device utilisation by exploiting opportunities for concurrent code execution within a model and through the use of ensembles of simulations. A novel hierarchical sub‐modelling approach is also presented which can be used to model certain types of recursive behaviours. This feature is shown to be essential in providing a mechanism to resolve competition for resources between agents within a parallel environment which would otherwise introduce race conditions. To understand the performance characteristics of the software, a benchmark model with millions of agents is used to explore the use of simulation ensembles and to parametrically investigate concurrent code execution within a model. Performance speedups are demonstrated of 3.5 and 10 respectively over a baseline GPU implementation. Our hierarchical sub‐modelling approach is used to demonstrate the implementation of a recursive algorithm to resolve competition of agent movement which occurs as a result of agent desire to simultaneously occupy discrete areas high in a ‘resource’. The algorithm is used to implement a classical socio‐economics model, Sugarscape, with populations of up to 16M agents.

ERGM: A multi-stage joint entity and relation extraction with global entity match

Joint entity and relation extraction is a fundamental and important task in the process of building knowledge graphs. At present, many researchers have proposed their own methods to solve this task, but these studies often have some limitations, such as irrelevant relation prediction, and lack of information interaction between the relation and entity. The complex model structure leads to inefficiency and does not make good use of the associations between the various subtasks. We propose a novel lightweight joint extraction model based on a global entity matching strategy. Specifically, the proposed framework contains three components: Relation Extraction Module, Relation Attention Based Entity Recognition Module and Global Entity Pairing Module. The Relation Extraction Module extracts candidate relations in the sentence, and the Relation Attention Based Entity Recognition Module introduces a relation attention mechanism based on the obtained candidate relations to fuse the information of the relations so as to better identify entities in the sentence. Then use entity vector representations to construct an affine transformation-based global entity matching matrix under a specific relation for triple extraction. Our model decomposes entity and relation extraction into three sub-tasks, which greatly simplifies the model structure, and the tasks are interrelated, making full use of the relevant information. In addition, we introduce a negative sampling strategy to alleviate the exposure bias problem of the model. We validate Our model on public dataset, it not only can effectively solve the triple overlap problem but also achieved a significant time performance speedup and effectively reduce memory occupation.

A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs

Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC)-based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. Different data placement policies may lead to different system performance, and finding an optimal data placement policy is a nontrivial problem. For instance, we show counter-intuitive results that traditional frequency and locality-based data placement strategy designed for CPU architecture leads to nonoptimal system performance in CPU-FPGA HMPSoCs. In this work, we first propose an automatic data placement framework for field programmable gate array (FPGA) kernels to determine whether each array object should be accessed via the on-chip BRAM, shared CPU L2-cache, or DDR memory to achieve the optimal performance. Moreover, we find that when the CPU kernel and the FPGA kernel are executed in parallel, memory contentions may degrade the performance and the optimal data placement policy designed for the FPGA kernel alone will not achieve the optimal overall system performance. In this article, we proposed to use cache partitioning to alleviate the impact brought by memory contentions. We extend the framework designed for FPGA by adding the cross-layer memory contentions analysis to automatically generate an optimal data placement policy and cache partitioning mechanism for the parallel executing kernels. The proposed data placement framework can be seamlessly integrated with the commercial Vivado HLS. The experimental results on the Zedboard platform show an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> performance speedup for FPGA kernels compared with a greedy-based allocation strategy. When FPGA kernels and CPU kernels are executed in parallel, the FPGA kernel and the CPU kernel have a performance speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.62\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> on average, respectively.

Privacy-Preserving Content-Based Similarity Detection Over in-the-Cloud Middleboxes

It is increasingly popular for cloud providers to offer middlebox service that supports content-based similarity detection for enterprises. However, redirecting network traffic to the cloud for such service raises security concerns. While trusted execution environments such as Intel SGX have emerged as a pragmatic solution for designing secure in-the-cloud middleboxes, it remains challenging to practically support content-based similarity detection. In this paper, we design a secure in-the-cloud middlebox system that can detect content-based similar flows in encrypted traffic dynamically. To cope with the constrained enclave memory, we adopt the caching technique and devise a compact index to increase the cache hit rate for effective similarity detection inside the enclave. We also present a parallel algorithm for performance speedup, with an efficient enclave thread management mechanism. Extensive evaluations demonstrate that the overhead of our system compared to native processing (without SGX) is limited to 2.1 <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex>$\times$</tex></formula> . Meanwhile, our tailored design can achieve up to <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex>$14.4\times$</tex></formula> better computational efficiency compared to simply moving the target functionality to the SGX enclave via existing popular library operating systems like Graphene-SGX and Occlum. Our secure system can achieve a normalized similarity detection precision of about 90%.

On-Line Fault Protection for ReRAM-Based Neural Networks

The emerging Resistive RAM (ReRAM) technology significantly boosts the performance and the energy efficiency of the deep learning accelerators (DLAs) via the Computing-in-Memory (CiM) architecture. However, ReRAM-based DLA also suffers a high occurrence rate of memory faults. How to detect and protect against the faults in ReRAM devices poses great challenges to ReRAM-based DLA design. In this work, we propose RRAMedy, an in-situ fault detection and network remedy framework for ReRAM-based DLAs. With the proposed Adversarial Example Testing, which is a lifetime on-device and on-line fault detection technique, it achieves high detection coverage of both hard faults and soft faults at a low run-time cost. In addition, it employs an edge-cloud collaborative model retraining method to tolerate the detected faults by leveraging the inherent fault-adaptive capability of DNNs. Meanwhile, to enable in-situ model remedy when the cloud assistance is absent due to security or overhead issues, we propose to accelerate the fault-masking retraining process on edge devices with parallelized Knowledge Transfer. Our experimental results show that the proposed fault detection technique achieves high fault detection accuracy and delivers real-time testing performance. Meanwhile, the proposed retraining approach greatly alleviates the accuracy degradation problem and achieves excellent performance speedups over the baselines.

TurboMGNN: Improving Concurrent GNN Training Tasks on GPU With Fine-Grained Kernel Fusion

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Graph Neural Networks</i> (GNN) have evolved as powerful models for graph representation learning. Many works have been proposed to support GNN training efficiently on GPU. However, these works only focus on a single GNN training task such as operator optimization, task scheduling, and programming model. Concurrent GNN training, which is needed in the applications such as neural network structure search, has not been explored yet. This work aims to improve the training efficiency of the concurrent GNN training tasks on GPU by developing fine-grained methods to fuse the kernels from different tasks. Specifically, we propose a fine-grained <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sparse Matrix Multiplication</i> (SpMM) based kernel fusion method to eliminate redundant accesses to graph data. In order to increase the fusion opportunity and reduce the synchronization cost, we further propose a novel technique to enable the fusion of the kernels in forward and backward propagation. Finally, in order to reduce the resource contention caused by the increased number of concurrent, heterogeneous GNN training tasks, we propose an adaptive strategy to group the tasks and match their operators according to resource contention. We have conducted extensive experiments, including kernel- and model-level benchmarks. The results show that the proposed methods can achieve up to 2.6X performance speedup.

Predicting Rainfall-induced Landslide Using Bee Colony Algorithm Based on Support Vector Regression

Objective: Natural disasters caused by landslides have done great harm to agricultural production, people's lives, and property. Considering the slope disaster caused by heavy rainfall, it is important to establish an early warning system to monitor rainfall disaster prevention. Huafang University Slope Sustainable Development Research Center (HUSSDRC) has set up a meteorological station equipped with many sensors to provide early warning for landslides in Taiwan. Since the amount of data collected will soon become very large, there is a need to implement strong parallel frameworks containing information from the meteorological station and the displacement of tiltmeters required to predict the landslides caused by rainfall. Apache Spark (AS) is a general framework that contains the parallel process engine for data analytics. In this study, a hybrid method is utilized to predict rainfall-induced landslides. The proposed method combines support vector regression (SVR) with an artificial bee colony (ABC) algorithm on the parallel platform of AS. For the proposed method, the RMSE is 0.562, and it is the best value among these compared approaches. Methods: The SVR together with an ABC algorithm is applied to predict rainfall-induced landslides on AS. The AS can perform parallel data analytics in memory to speed up performance. However, it is hard to set up the best parameters for SVR. Thereafter, the ABC algorithm is utilized to search for the best parameters for SVR. Results: Compared with other methods, the proposed method results provide the smallest root mean square error (RMSE) for predicting rainfall-induced landslides. Conclusion: A hybrid method is proposed to predict rainfall-induced landslides. The proposed hybrid method is based on the parallel platform of AS in which SVR predicts the rainfall-induced landslides, and the ABC algorithm adjusts the best values of parameters for SVR. The comparison of RMSE for the method with existing approaches shows that the method indeed has the best value among compared approaches.

PARALLEL PROCESSING OUTCOMES OF E-ABDULRAZZAQ ALGORITHM USING MULTI-CORE TECHNIQUE

The string matching problem is considered one of the substantial problems in the fields of computer science like speech and pattern recognition, signal and image processing, and artificial intelligence (AI). The increase in the speedup of performance is considered an important factor in meeting the growth rate of databases, Subsequently, one of the determinations to address this issue is the parallelization for exact string matching algorithms. In this study, the E-Abdulrazzaq string matching algorithm is chosen to be executed with the multi-core environment utilizing the OpenMP paradigm which can be utilized to decrease the execution time and increase the speedup of the algorithm. The parallelization algorithm got positive results within the parallel execution time, and excellent speeding-up capabilities, in comparison to the successive result. The Protein database showed optimal results in parallel execution time, and when utilizing short and long pattern lengths. The DNA database showed optimal speedup execution when utilizing short and long pattern lengths, while no specific database obtained the worst results.

On extending Amdahl’s law to learn computer performance

The problem of learning parallel computer performance is investigated in the context of multicore processors. Given a fixed workload, the effect of varying system configuration on performance is sought. Conventionally, the performance speedup due to a single resource enhancement is formulated using Amdahl’s law. However, in case of multiple configurable resources the conventional formulation results in several disconnected speedup equations that cannot be combined together to determine the overall speedup. To solve this problem, we propose to (1) extend Amdahl’s law to accommodate multiple configurable resources into the overall speedup equation, and (2) transform the speedup equation into a multivariable regression problem suitable for machine learning. Using experimental data from fifty-eight tests spanning two benchmarks (SPECCPU 2017 and PCMark 10) and four hardware platforms (Intel Xeon 8180M, AMD EPYC 7702P, Intel CoffeeLake 8700K, and AMD Ryzen 3900X), analytical models are developed and cross-validated. Findings indicate that in most cases, the models result in an average cross-validated accuracy higher than 95%, thereby validating the proposed extension of Amdahl’s law. The proposed methodology enables rapid generation of multivariable analytical models to support future industrial development, optimization, and simulation needs.

Storage-Heterogeneity Aware Task-based Programming Models to Optimize I/O Intensive Applications

Task-based programming models have enabled the optimized execution of the computation workloads of applications. These programming models can take advantage of large-scale distributed infrastructures by allowing the parallel and distributed execution of applications in high-level work components called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tasks</i> . Nevertheless, in the era of Big Data and Exascale, the amount of data produced by modern scientific applications has already surpassed terabytes and is rapidly increasing. Hence, I/O performance became the bottleneck to overcome in order to achieve more total performance improvement. New storage technologies offer higher bandwidth and faster solutions than traditional Parallel File Systems (PFS). Such storage devices are deployed in modern day infrastructures to boost I/O performance by offering a fast layer that absorbs the generated data. Therefore, it is necessary for any programming model targeting more performance to manage this heterogeneity and take advantage of it to improve the I/O performance of applications. Towards this goal, we propose in this article a set of programming model capabilities that we refer to as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Storage-Heterogeneity Awareness</i> . Such capabilities include: (i) abstracting the heterogeneity of storage systems, and (ii) optimizing I/O performance by supporting dedicated I/O schedulers and an automatic data flushing technique. The evaluation section of this article presents the performance results of different applications on the MareNostrum CTE-Power heterogeneous storage cluster. Our experiments demonstrate that a storage-heterogeneity aware programming model can achieve up to almost 5x I/O performance speedup and 48% total time improvement compared to the reference PFS-based usage of the execution infrastructure.

A sparse matrix vector multiplication accelerator based on high-bandwidth memory

Sparse matrix–vector multiplication (SpMV) is an important kernel that is widely used in science and engineering applications. The features of SpMV, such as high memory-intensiveness and many different access patterns, cause the performance of SpMV to be bounded by the limited bandwidth between memory and processing units. Processing in memory (PIM) is a novel architecture used to overcome the bandwidth bottleneck by shortening the distance between processing elements (PE) and memory. In this paper, we propose a PIM-structure SpMV accelerator based on high-bandwidth memory (HBM). To make full use of the high bandwidth provided by HBM, we design a highly parallel PE array and implement a high-frequency pipeline inside the PE to hide the latency of reading matrix elements from HBM. For each PE, we integrate an L1 cache to exploit the data locality in the vector. We propose two data layout strategies, namely a row merging algorithm to exploit the inter-row data locality and a row assignment algorithm to achieve workload balance among PEs. Our design is implemented using a field programmable gate array (FPGA) card with 8GB HBM2 memory. Compared to the baseline central processing unit (CPU) SpMV implementation, our accelerator can obtain a 5.24x performance speedup on average.

FastGeodis: Fast Generalised Geodesic Distance Transform

The FastGeodis package provides an efficient implementation for computing Geodesic and Euclidean distance transforms (or a mixture of both), targeting efficient utilisation of CPU and GPU hardware. In particular, it implements the paralellisable raster scan method from Criminisi et al. (2009), where elements in a row (2D) or plane (3D) can be computed with parallel threads. This package is able to handle 2D as well as 3D data, where it achieves up to a 20x speedup on a CPU and up to a 74x speedup on a GPU as compared to an existing open-source library (Wang, 2020) that uses a non-parallelisable single-thread CPU implementation. The performance speedups reported here were evaluated using 3D volume data on an Nvidia GeForce Titan X (12 GB) with a 6-Core Intel Xeon E5-1650 CPU. Further in-depth comparison of performance improvements are discussed in the FastGeodis documentation: https://fastgeodis.readthedocs.io

SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference

In this paper we propose SECDA-TFLite, a new open source toolkit for developing DNN hardware accelerators integrated within the TFLite framework. The toolkit leverages the principles of SECDA, a hardware/software co-design methodology, to reduce the design time of optimized DNN inference accelerators on edge devices with FPGAs. With SECDA-TFLite, we reduce the initial setup costs associated with integrating a new accelerator design within a target DNN framework, allowing developers to focus on the design. SECDA-TFLite also includes modules for cost-effective SystemC simulation, profiling, and AXI-based data communication. As a case study, we use SECDA-TFLite to develop and evaluate three accelerator designs across seven common CNN models and two BERT-based models against an ARM A9 CPU-only baseline, achieving an average performance speedup across models of up to 3.4× for the CNN models and of up to 2.5× for the BERT-based models. Our code is available at https://github.com/gicLAB/SECDA-TFLite.

Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning

Homomorphic encryption (HE) is the ultimate tool for performing secure computations even in untrusted environments. Application of HE for deep learning (DL) inference is an active area of research, given the fact that DL models are often deployed in untrusted environments (e.g., third-party servers) yet inferring on private data. However, existing HE libraries [somewhat (SWHE), leveled (LHE) or fully homomorphic (FHE)] suffer from extensive computational and memory overhead. Few performance optimized high-speed homomorphic libraries are either suffering from certain approximation issues leading to decryption errors or proven to be insecure according to recent published attacks. In this article, we propose architectural tricks to achieve performance speedup for encrypted DL inference developed with exact HE schemes without any approximation or decryption error in homomorphic computations. The main idea is to apply quantization and suitable data packing in the form of bitslicing to reduce the costly noise handling operation, Bootstrapping while achieving a functionally correct and highly parallel DL pipeline with a moderate memory footprint. Experimental evaluation on the MNIST dataset shows a significant ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$37\times$ </tex-math></inline-formula> ) speedup over the nonbitsliced versions of the same architecture. Low memory bandwidths (700 MB) of our design pipelines further highlight their promise toward scaling over larger gamut of Edge-AI analytics use cases.

A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore Processors

Conventional electronic memory hierarchies are intrinsically limited in their ability to overcome the memory wall due to scaling constraints. Optical caches and interconnects can mitigate these constraints, and enable processors to reach performance and energy efficiency unattainable by purely electronic means. However, the promised benefits cannot be realized through a simple replacement process; to reach its full potential, the architecture needs to be holistically redesigned. This article proposes Pho$, an opto-electronic memory hierarchy architecture for multicores. Pho$ replaces conventional core-private electronic caches with a large shared optical L1 built with optical SRAMs. The shared optical cache is supported by Pho$Net, a novel hybrid MWSR/R-SWMR optical NoC that provides low-latency and high-bandwidth communication between the electronic cores and the shared optical L1 at low optical loss. Pho$Net’s unique network arbitration protocol seamlessly co-arbitrates the request and reply sub-networks and facilitates cache requests and replies that optimize for the common case of cache hits. Through Pho$ we solve the problems that render previous designs impractical. Our results show that Pho$ achieves on average 1.41× performance speedup (3.89× max) and 31% lower energy-delay product (90% max) against conventional designs. Moreover, the Pho$Net optical NoC for core-cache communication consumes 70% less power compared to directly applying previously proposed optical NoC architectures.