Performance Of Printed Circuit Board Research Articles

Near end and Far end Crosstalk reduction in High-Speed Signaling Channel with Periodical Spiral Resonator Defected Microstriplines in a High Performance Printed Circuit Board

Near end and Far end Crosstalk reduction in High-Speed Signaling Channel with Periodical Spiral Resonator Defected Microstriplines in a High Performance Printed Circuit Board

Innovative Theory of Low-Pass NGD via-Hole-Ground Circuit

The via ground (GND) structure constitutes one of the most useful elements for designing high performance printed circuit boards (PCBs). The electrical interconnections with vias become key regular solutions for the implementation of various electronic functions. However, so far, the vias are never being used for designing negative group delay (NGD) circuit. To answer this curious question, an original study on the design feasibility of low-pass NGD function with via ground is introduced in the present paper. After the topological description, the NGD analysis in function of the via parameters is established. The design equations allowing to synthesize the via in function of NGD function specifications are formulated. The developed NGD theory is verified with comparisons between calculations and simulations with a commercial tool. As expected, NGD value in order of hundred-picoseconds over hundred-megahertz cut-off frequencies is obtained with good agreement between the theoretical model and simulation. Furthermore, time domain analyses confirm that the via NGD structure enables to generate output signals in time-advance of arbitrary waveform input signals presenting limited bandwidth.

Numerical Investigation on the Effect of Squeegee Angle during Stencil Printing Process

The high requirement of smaller size, lighter weight, and high performance Printed Circuit Board (PCB) in electronic packaging has contributed to the wide application of stencil printing for soldering process. However, during stencil printing stage contributes major concern compared to other stages in Surface Mount Technology (SMT). Unsuitable process parameters can cause the soldering defects that can lead to product failure in further processes in the production line. An investigation has been conducted to predict the real-time observation of solder paste Sn96.5Ag3.0Cu0.5 (SAC305) filling process into stencil apertures as well as print quality in stencil printing by using Computational Fluid Dynamics (CFD) approach. A 3-Dimensional stencil printing model was developed and simulated in ANSYS Fluent 17 of different angles. It is found that squeegee angle 60° to 80° has potential to obtain the good print quality of solder paste.

Correlating Interconnect Stress Test and Accelerated Thermal Cycling for Accessing the Reliabilities of High Performance Printed Circuit Boards

Understanding the failure mechanism of a plated through hole (PTH) is essential for a complete picture of their life span, and hence for the continued electronic reliability prediction and development of high performance printed circuit boards. This paper presents the efficacy of establishing a correlation between interconnect stress test (IST) and accelerated thermal cycling (ATC) data on standard high performance coupons. In accord with the observation in PTH micro-sectioning, a PTH failure mechanism is proposed based on the thermal expansion-induced shearing at the copper-resin interface. The PTH cycle to failure data from the two methodologies, IST and ATC, are correlated. In terms of the glass transition temperature, a linear relationship exists between two different data sets. It is also demonstrated that the base material thermal property and PTH sizes are the two essential factors determining the reliability of a PTH. Furthermore, a life stress model is created to predict the life time of a coupon at a particular temperature level.

Multifactor performance measure model with an application to printed circuit board industry

The research described in this paper contains two parts. The first part is to present an empirical investigation where financial index is considered to measure the printed circuit board performance. The second part is to examine the effects of financial index on sales and gross margin. The technique of Data Envelopment Analysis is utilised to derive the efficiency and multiple regression analysis to disclose the effects. There were remarkable results: (1) the averaged efficiency was 0.746 which, generally speaking, did not show a good performance, (2) PCB manufacturers in the group of Single-Sided Boards/Double-Sided Boards and Multi-Layer Boards manufacturers performed average efficiency was 0.7784, (3) PCB manufacturers in the group of Flexible Print Circuit (FPC) performed average efficiency was 0.8492, (4) current assets, the number of employees and operating expenses showed significant effects on both the sales and gross margin. Other research findings were addressed and discussed in this research also.

SAVIA, an advanced multi‐layer parallel lamination technique for high density, high performance printed circuit boards

PurposeTo review a newly developed PCB fabrication process based on a parallel lamination technique.Design/methodology/approachThis paper has been written to introduce the SAVIA process, a new parallel lamination technique for PCB fabrication. The basic concept of the SAVIA process has been described along with the individual process steps and the reliability issues. The advantages of SAVIA process have been also discussed in both economical and technological aspects.FindingsIt was found that the parallel lamination technique, a key process for SAVIA, was not only highly flexible and reliable but also a cost‐effective fabrication method for high performance PCB. With the SAVIA process, manufacturing lead‐times can be substantially reduced due to the nature of the parallel processing. It was also confirmed that a highly reliable metal alloy interconnection was created between the core and the adhesive layers during the lamination process. The formed metal alloy contacts showed excellent electrical and physical characteristics. The between layers was precise.Originality/valueThe value of this paper is to introduce a novel PCB fabrication process based on a parallel lamination technique that is superior to conventional build‐up processes from both technological and economical viewpoints. By applying a parallel lamination technique, it is expected that fabrication costs can be lowered due to reductions in manufacturing lead‐time.

Surface activated bonding of LCP/Cu for electronic packaging

A lamination technique for liquid crystal polymer (LCP)/Cu was developed for high speed and high performance printed circuit boards (PCB). This approach was accomplished by using a modified surface activated bonding (SAB) process to achieve enhanced adhesion and a smooth interface. Systematic investigation of peel strength of four categories of samples, namely “as bonded”, “annealed”, “Cu-deposited”, and “Cu-deposited and annealed” showed highest peel strength in the “Cu-deposited and annealed” sample. Significant improvements in adhesion were observed in the samples cleaned with argon-radio frequency (Ar-rf) plasma (“as bonded” samples) followed by Cu deposition on LCP, which were heated after bonding in low vacuum pressure at 240∘C (about 70–75 times higher than that of “as bonded”). XPS analyses on peeled surfaces of the “Cu-deposited and annealed” sample reveal bulk fracture in the LCP. Threefold lower loss in conduction of SAB processed laminate than that of conventional heat laminate was most likely due to smooth interface of the SAB processed laminate (surface roughness was ninefold lower than that of conventional heat laminate). A plausible adhesion mechanism of Cu/LCP might be due to bonding of Cu adhesion sites to plasma induced dangling sites of LCP surface, and thermal reconstruction of Cu deposited layers.

High performance printed circuit boards [Book Reviews

High performance printed circuit boards [Book Reviews

Improved Printed Circuit Reliability by Risk Site Analysis

The circuit elements of every printed circuit board have the potential for failure during test and/or use. These failures can occur by forming short‐circuits between adjacent circuit elements, or by forming open‐circuits in the conductors. The risk sites can be identified by type, and the total number enumerated by manual inspection of the photolithographic masks used to fabricate the printed circuit layers. However, the circuit density of high performance printed circuit boards has become so great that meaningful manual analysis has become impractical. A more effective method is to use special graphics programs to analyse the computer‐aided design (CAD) data. The methodology developed to perform the CAD analysis of high performance printed circuit boards for short‐circuits utilises two powerful computer graphic tools: the Interactive Graphics System and the Unified Shapes Checking system. Test data for open‐circuits are generated using specially written alphanumeric routines. The data can be used for stress testing the printed circuit boards by wiring up special test modules that are plugged into the boards and then placing the boards into environmental test chambers. The printed circuits are checked for short‐circuits by putting them into groups that have no risk of shorting to each other (zero risk), and placing the groups in parallel under an electrical potential. The flow of current between the groups would indicate a short‐circuit. Similarly, the printed circuits can be checked for open‐circuits, by stringing them together into groups in series, and measuring the changes in resistance under thermal stress. Both types of test data can also be used for in‐process testing.