Improved Printed Circuit Reliability by Risk Site Analysis

Abstract

The circuit elements of every printed circuit board have the potential for failure during test and/or use. These failures can occur by forming short‐circuits between adjacent circuit elements, or by forming open‐circuits in the conductors. The risk sites can be identified by type, and the total number enumerated by manual inspection of the photolithographic masks used to fabricate the printed circuit layers. However, the circuit density of high performance printed circuit boards has become so great that meaningful manual analysis has become impractical. A more effective method is to use special graphics programs to analyse the computer‐aided design (CAD) data. The methodology developed to perform the CAD analysis of high performance printed circuit boards for short‐circuits utilises two powerful computer graphic tools: the Interactive Graphics System and the Unified Shapes Checking system. Test data for open‐circuits are generated using specially written alphanumeric routines. The data can be used for stress testing the printed circuit boards by wiring up special test modules that are plugged into the boards and then placing the boards into environmental test chambers. The printed circuits are checked for short‐circuits by putting them into groups that have no risk of shorting to each other (zero risk), and placing the groups in parallel under an electrical potential. The flow of current between the groups would indicate a short‐circuit. Similarly, the printed circuits can be checked for open‐circuits, by stringing them together into groups in series, and measuring the changes in resistance under thermal stress. Both types of test data can also be used for in‐process testing.