Abstract

Increase in the cost of printed circuit board (PCB) with the increase in layer count has led to the design of PCB stack-ups that have broadside coupled signals. Broadside coupling of signals in adjacent layers also leads to crosstalk that can be sometimes difficult to model and quantify in terms of its impact on receiver eye opening. The difficulty stems from the fact that in most boards, broadside coupling occurs between the signal traces at various angles and at multiple instances. The challenges involved in modeling include generating models for the broadside coupled section quickly without the overhead of time consuming full-wave simulations. Full wave simulations are time and memory intensive especially for coupled traces at an angle and real board designs can have hundreds of them. The simulation challenges include predicting the impact of crosstalk on bit error rate (BER) accurately. In this paper, the focus is on alleviating the modeling challenges by using fast equivalent per unit length (Eq. PUL) [1, 10] resistance, inductance, conductance, capacitance (RLGC) method for the broadside coupled traces crossing at an angle and to resolve the simulation challenge by seamlessly integrating the models into statistical simulation approach that can quantify the eye opening at various BERs that would help electrical designers to come up with set of design and routing guidelines that can save PCB cost and at the same time maintain electrical integrity.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.