Performance Of Solid State Drives Research Articles

Performance and reliability concern scheme for efficient garbage collection and wear leveling on flash memory-based solid state disk

In the near future, data is expected to double in every two years, which translates to more than one terabyte of data for every person on earth. The difficulty of storing and fetching required data from data centers and servers will consequently increase. As a result, significant attention has been given to the flash memory-based solid state drive (SSD) from consumer electronics companies, which has begun to replace the existing hard disk drive and is highly likely to be used as a storage unit for most of consumer electronics to achieve low power consumption. In contrast to traditional disk, SSD uses semiconductor chips to store data. This structure enjoys original technical characteristics, including low power consumption, shock resistance, and high performance in random access. Such features can overcome the shortcomings of magnetic disks. However, flash memory, the basic unit of SSD, has many distinctive characteristics that cause various challenges. Flash memory does not support updating in the place method. A write operation can be performed only on an empty or erased unit, making the process more time-consuming. Moreover, each storage unit has a limited number of erase cycles, after which the block becomes invalid. This research proposes a new scheme called performance and reliability concern to increase the reliability and performance of SSDs. The eligibility of the proposed scheme is proven through EagleTree simulator. The scheme is also compared with other state-of-the-art techniques in terms of effectiveness and efficiency. Experimental results show that the proposed scheme provides sufficient performance and reliability for SSD.

Performance Evaluation of Dynamic Page Allocation Strategies in SSDs

Solid-state drives (SSDs) with tens of NAND flash chips and highly parallel architectures are widely used in enterprise and client storage systems. As any write operation in NAND flash is preceded by a slow erase operation, an out-of-place update mechanism is used to distribute writes through SSD storage space to postpone erase operations as far as possible. SSD controllers use a mapping table along with a specific allocation strategy to map logical host addresses to physical page addresses within storage space. The allocation strategy is further responsible for accelerating I/O operations through better striping of physical addresses over SSD parallel resources. Proposals already exist for using static logical-to-physical address mapping that does not balance the I/O traffic load within the SSD, and its efficiency highly depends on access patterns. A more balanced distribution of I/O operations is to alternate resource allocation in a round-robin manner irrespective of logical addresses. The number of resources that can be dynamically allocated in this fashion is defined as the degree of freedom, and to the best of our knowledge, there has been no research thus far to show what happens if different degrees of freedom are used in allocation strategy. This article explores the possibility of using dynamic resource allocation and identifies key design opportunities that it presents to improve SSD performance. Specifically, using steady-state analysis of SSDs, we show that dynamism helps to mitigate performance and endurance overheads of garbage collection. Our steady-state experiments indicate that midrange/high-end SSDs with dynamic allocation can provide I/O operations per second (IOPS) improvement of up to 3.3x/9.6x, response time improvement of up to 56%/32%, and about 88%/96% average reduction in the standard deviation of erase counts of NAND flash blocks.

Internal Parallelism of Flash Memory-Based Solid-State Drives

A unique merit of a solid-state drive (SSD) is its internal parallelism . In this article, we present a set of comprehensive studies on understanding and exploiting internal parallelism of SSDs. Through extensive experiments and thorough analysis, we show that exploiting internal parallelism of SSDs can not only substantially improve input/output (I/O) performance but also may lead to some surprising side effects and dynamics. For example, we find that with parallel I/Os, SSD performance is no longer highly sensitive to access patterns (random or sequential), but rather to other factors, such as data access interferences and physical data layout. Many of our prior understandings about SSDs also need to be reconsidered. For example, we find that with parallel I/Os, write performance could outperform reads and is largely independent of access patterns, which is opposite to our long-existing common understanding about slow random writes on SSDs. We have also observed a strong interference between concurrent reads and writes as well as the impact of physical data layout to parallel I/O performance. Based on these findings, we present a set of case studies in database management systems, a typical data-intensive application. Our case studies show that exploiting internal parallelism is not only the key to enhancing application performance, and more importantly, it also fundamentally changes the equation for optimizing applications. This calls for a careful reconsideration of various aspects in application and system designs. Furthermore, we give a set of experimental studies on new-generation SSDs and the interaction between internal and external parallelism in an SSD-based Redundant Array of Independent Disks (RAID) storage. With these critical findings, we finally make a set of recommendations to system architects and application designers for effectively exploiting internal parallelism.

Exploiting Sequential and Temporal Localities to Improve Performance of NAND Flash-Based SSDs

NAND flash-based Solid-State Drives (SSDs) are becoming a viable alternative as a secondary storage solution for many computing systems. Since the physical characteristics of NAND flash memory are different from conventional Hard-Disk Drives (HDDs), flash-based SSDs usually employ an intermediate software layer, called a Flash Translation Layer (FTL). The FTL runs several firmware algorithms for logical-to-physical mapping, I/O interleaving, garbage collection, wear-leveling, and so on. These FTL algorithms not only have a great effect on storage performance and lifetime, but also determine hardware cost and data integrity. In general, a hybrid FTL scheme has been widely used in mobile devices because it exhibits high performance and high data integrity at a low hardware cost. Recently, a demand-based FTL based on page-level mapping has been rapidly adopted in high-performance SSDs. The demand-based FTL more effectively exploits the device-level parallelism than the hybrid FTL and requires a small amount of memory by keeping only popular mapping entries in DRAM. Because of this caching mechanism, however, the demand-based FTL is not robust enough for power failures and requires extra reads to fetch missing mapping entries from NAND flash. In this article, we propose a new flash translation layer called LAST++. The proposed LAST++ scheme is based on the hybrid FTL, thus it has the inherent benefits of the hybrid FTL, including low resource requirements, strong robustness for power failures, and high read performance. By effectively exploiting the locality of I/O references, LAST++ increases device-level parallelism and reduces garbage collection overheads. This leads to a great improvement of I/O performance and makes it possible to overcome the limitations of the hybrid FTL. Our experimental results show that LAST++ outperforms the demand-based FTL by 27% for writes and 7% for reads, on average, while offering higher robustness against sudden power failures. LAST++ also improves write performance by 39%, on average, over the existing hybrid FTL.

Failure Analysis and Reliability Study of NAND Flash-Based Solid State Drives

<p>The research focuses on conducting failure analysis and reliability study to understand and analyze the root cause of Quality, Endurance component Reliability Demonstration Test (RDT) failures and determine SSD performance capability. It addresses essential challenges in developing techniques that utilize solid-state memory technologies (with emphasis on NAND flash memory) from device, circuit, architecture, and system perspectives. These challenges include not only the performance degradation arising from the physical nature of NAND flash memory, e.g., the inability to modify data in-place read/write performance asymmetry, and slow and constrained erase functionality, but also the reliability drawbacks that limits Solid State Drives (SSDs) performance. In order to understand the nature of failures, a Fault Tree Analysis (FTA) was performed that identified the potential causes of component failures. In the course of this research, significant data gathering and analysis effort was carried out that led to a systematic evaluation of the components under consideration. </p>

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality

NAND flash-based solid-state drives (SSDs), which can serve as the caches of hard disk drives, have gained popularity in large-scale, high-performance storage. A type of advanced error correction code for SSDs, low-density parity-check (LDPC), is required to mitigate a considerable number of errors in the raw data of NAND flash. However, LDPC imposes read performanceoverhead due to the complex decoding procedure of LDPC. In this paper, we propose an error-correcting cache (EC-Cache) that exploits “ error locality ”, a characteristic of NAND flash memory, to improve the read performance of SSDs. We use the term “error locality” to refer to the property that the majority of errors in reads to the same flash page appear at the same positions until thepage is erased. By caching detected errors, we can correct a significant portion of errors in the requested flash page prior to the LDPC decoding process. This design significantly reduces LDPC decoding overhead because the latency of LDPC is correlated with thenumber of errors in the input data. We conduct experiments, including flash characterization, LDPC simulation, and SSD simulation,to evaluate EC-Cache. The experimental results demonstrate that EC-Cache can improve the read performance of LDPC-based SSDs by up to $2.6\times$ .

Effective Lifetime-Aware Dynamic Throttling for NAND Flash-Based SSDs

NAND flash-based solid-state drives (SSDs) are increasingly popular in enterprise server systems because of their advantages over hard disk drives such as higher performance and lower power consumption. However, the decreasing write endurance and the unpredictable lifetime remains to be a serious obstacle to their wider adoption in enterprise systems. In this paper, we propose effective lifetime-aware dynamic throttling, called LADY, which guarantees the required storage lifetime by intentionally throttling the write performance of SSDs with consideration of the effective write endurance of NAND flash memory. Unlike existing static throttling, LADY makes throttling decisions based on the characteristics of a workload so that the required SSD lifetime can be guaranteed with less performance degradation. LADY also exploits the improvement on write endurance depending on the NAND program speed and the recovery effects of floating-gate transistors, thereby maximally utilizing the available write endurance of NAND flash while mitigating the decreasing write endurance problem. Our experimental results show that LADY improves write performance by 4.7x with small write response time variations over existing static throttling while guaranteeing the required SSD lifetime.

Supporting System Consistency with Differential Transactions in Flash-Based SSDs

Embedded transaction design inside solid state drives (SSDs) is an attractive way to support system consistency with low overhead due to the no-overwrite property of flash memory. Recent research proposes shadow paging variants to reduce write traffic to SSDs for longer lifetime while leveraging the random performance of SSDs. However, writes in transactions usually are small, and the page-aligned shadow paging protocols still incur high write amplification, which hurts SSD lifetime. In this paper, we propose an embedded transaction protocol, DiffTx, which differentially logs partial page updates in a write-ahead logging way and writes full page updates in a shadow paging way, aiming at low write amplification. DiffTx further improves transaction performance using two techniques. First, by clustering mapping metadata of full page updates with differential data of partial page updates in a single record, DiffTx tracks pages of each transaction at low overhead. Second, DiffTx removes the write ordering on commit by delaying the completeness check of writes, leveraging the clean-state write property of flash memory. Experiments show that DiffTx improves throughput by 25.9 percent and halves write traffic on average compared to TxFlash, a typical embedded transaction protocol for flash memory.

LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives

There is an increasing demand for the solid-state drive (SSD) due to its high speed, low power, and high reliability. However, random write intensive workload is not good for the SSD performance due to the inherent characteristics of the NAND flash memory. As the garbage collection (GC) causes the bottleneck of the SSD write performance due to the page-copy overhead, a NAND flash aware system is proposed to improve the SSD performance with a scheme called logical block address (LBA) scrambler. In the proposed scheme, new data are actively written to the fragmented pages in the next erase block. As a result, the number of valid pages inside the block is reduced when the block is recycled. Considering that there are NAND flash blocks full of valid pages in the proposed scheme, a skipping full block round robin (SFB_RR) GC policy is proposed, showing 0%–58% performance improvement compared with the RR GC policy. Furthermore, certain valid pages in the SSD have obsolete data due to the logical address remapping of the LBA scrambler, which cannot be invalidated by the conventional TRIM command, thus a SWEEP command is introduced. With the SWEEP command, maximum 12% additional SSD performance gain is obtained. From the experimental results, 35%–394% performance improvement, 27%–56% energy consumption reduction, and 25%–55% endurance enhancement are achieved by the proposed LBA scrambler scheme + SFB_RR GC policy + SWEEP command support, compared with the conventional SSD.

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives

Currently available electronic design automation tools for design space exploration of solid state drives (SSDs) are not able to assess: 1) the device architecture inefficiencies; 2) architecture overdesign for a target performance; and 3) performance degradation caused by the disk usage. These tools feature either an overly high abstraction modeling strategy or lack the required flexibility to perform design exploration. To overcome these problems, this paper proposes SSDExplorer, a tool for fine-grained yet reasonably fast design space exploration of different SSD architectures highlighting possible bottlenecks. To prove its accuracy SSDExplorer has been validated with two real SSDs. SSDExplorer efficiency has been assessed by evaluating the impact of the NAND flash read retry algorithm impact on the SSD performance as a function of its internal architecture.

High-Performance and Lightweight Transaction Support in Flash-Based SSDs

Flash memory has accelerated the architectural evolution of storage systems with its unique characteristics compared to magnetic disks. The no-overwrite property of flash memory naturally supports transactions, a commonly used mechanism in systems to provide consistency. However, existing embedded transaction designs in flash-based Solid State Drives (SSDs) either limit the transaction concurrency or introduce high overhead in tracking transaction states. This leads to low or unstable SSD performance. In this paper, we propose a transactional SSD (TxSSD) architecture, LightTx, to enable better concurrency and low overhead. First, LightTx improves transaction concurrency arbitrarily by using a page-independent commit protocol. Second, LightTx tracks the recent updates by leveraging the near-log-structured update property of SSDs and periodically retires dead transactions to reduce the transaction state tracking cost. Experiments show that LightTx achieves nearly the lowest overhead in garbage collection, memory consumption and mapping persistence compared to existing embedded transaction designs. LightTx also provides up to 20.6 percent performance improvement due to improved transaction concurrency.

Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives

Three-dimensional nand memory devices based on charge trapping (CT) technology represent the most promising solution for hyperscaled solid-state drives (SSDs). However, the intrinsic low reliability offered by that storage medium leads to a high number of errors requiring an extensive use of complex error correction codes (ECCs) and advanced read algorithms such as read retry. This materializes in an overall reduction in the SSD's QoS. In order to limit the error number, enhanced program algorithms that are able to improve the reliability figures of CT memory devices have been introduced. In this paper, the impact of such program algorithms combined with read retry and the ECC is experimentally characterized on CT- nand arrays. The results are then exploited for cosimulations at the system level, assessing the reliability, performance, and QoS of future SSDs integrating CT-based memory devices.

SSD-Tailor: Automated Customization System for Solid-State Drives

Enterprise servers require customized solid-state drives (SSDs) to satisfy their specialized I/O performance and reliability requirements. For effective use of SSDs for enterprise purposes, SSDs must be designed considering requirements such as those related to performance, lifetime, and cost constraints. However, SSDs have numerous hardware and software design options, such as flash memory types and block allocation methods, which have not been well analyzed yet, but on which the SSD performance depends. Furthermore, there is no methodology for determining the optimal design for a particular I/O workload. This paper proposes SSD-Tailor, a customization tool for SSDs. SSD-Tailor determines a near-optimal set of design options for a given workload. SSD designers can use SSD-Tailor to customize SSDs in the early design stage to meet the customer requirements. We evaluate SSD-Tailor with nine I/O workload traces collected from real-world enterprise servers. We observe that SSD-Tailor finds near-optimal SSD designs for these workloads by exploring only about 1% of the entire set of design candidates. We also show that the near-optimal designs increase the average I/O operations per second by up to 17% and decrease the average response time by up to 163% as compared to an SSD with a general design.

Zombie Chasing: Efficient Flash Management Considering Dirty Data in the Buffer Cache

This paper presents a novel technique, called Zombie Chasing, for efficient flash management in solid state drives (SSDs). Due to the unique characteristics of NAND flash memory, SSDs need to accurately understand the liveness of the data stored in themselves. Recently, the TRIM command has been introduced to notify SSDs of dead data caused by file deletions, which otherwise could not be tracked by SSDs. This paper goes one step further and proposes a new liveness state, called the zombie state, to denote live data that will be dead shortly due to the corresponding dirty data in the buffer cache. We also devise new zombie-aware garbage collection algorithms which utilize the information about such zombie data inside SSDs. To evaluate Zombie Chasing, we implement zombie-aware garbage collection algorithms in the prototype SSD and modify the Linux kernel and the Oracle DBMS to deliver the information on the zombie data to the prototype SSD. Through comprehensive evaluations using our in-house micro-benchmark and the TPC-C benchmark, we observe that Zombie Chasing improves SSD performance effectively by reducing garbage collection overhead. Especially, our evaluation with the TPC-C benchmark on the Oracle DBMS shows that Zombie Chasing enhances the Transactions Per Second (TPS) value by up to 22% with negligible overhead.

Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive

A NAND flash memory/storage-class memory (SCM) hybrid solid-state drive (SSD) can achieve higher performance than the conventional NAND flash-only SSD. Error-correcting codes (ECCs) are applied to the SSD to correct bit errors occurring inside the NAND flash and SCM. To correct more bit errors, the stronger ECC is required and the ECC latency increases. This paper evaluates the relation between the performance and the reliability of the NAND flash/SCM hybrid SSD. First, how the ECC latency impacts the SSD performance is analyzed. Then, the SSD performances are evaluated with various data-access patterns. The ECC effect is significantly different among the data-access patterns. Moreover, four scenarios of the SCM reliability are established and the performances are evaluated with the four data-access patterns. When the SCM reliability becomes high, the decrease in the throughput due to the ECC for SCM becomes significantly small. Finally, by setting the acceptable SSD performance, the acceptable bit-error rate (BER) of the SCM is evaluated. The SCM BER can be as high as around 0.9%.

Storage Management Method for Hybrid Storage System to Reduce Extent Fragmentation

A hybrid storage system consists of a small and fast solid state drive (SSD) and one or more slow and large hard disk drives (HDD). The purpose of a hybrid storage sys-tem is to exploit the IO performance of SSDs to enhance the overall IO performance with comparatively low cost. In a hybrid storage system, since the size of a SSD is small, the storage utilization for the SSD is very important to guarantee the performance of a hybrid storage system. Some existing hybrid storages use extents to manage a large storage efficiently. However, they cause an extent fragmentation problem. The extent fragmentation reduces the SSD utilization and the overall performance of a hybrid storage system. In this paper, to solve the problem we propose a new mapping method that uses different size of IO unit for SSD and HDDs. Also, we perform simulations to show that our proposed method guarantees better SSD utilization than existing methods.

Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD

Storage class memories (SCMs) are fast and energy-efficient solid-state memories with high endurance. However, the bit cost of SCM is higher than that of NAND flash memory due to its relative production immaturity. As a cost-effective alternative to replace the conventional NAND flash-only solid-state drive (SSD), the hybrid SCM/MLC NAND SSD is a promising next generation storage solution. It is already understood that SCM capacity requirement depends on the workload characteristics. However, the optimum SCM capacity is also determined by the latency parameters of the SCM chips themselves. Therefore, in this paper, the dependencies of SCM capacity on SCM chip latency parameters are analyzed for the hybrid SCM/MLC NAND flash SSD. From the experimental results, increasing SCM capacity to accelerate the SSD performance is feasible when the write and read latencies of the SCM are below 1 μs. Furthermore, SSD energy consumption is more dependent on write rather than read latency. Finally, optimistic and pessimistic models of SCM area cost are considered in order to optimize the cost-efficiency of the SCM chip design in the hybrid SCM/MLC NAND SSD. According to the SCM area cost models, a SCM:NAND capacity ratio of at least 1.5% with a SCM read latency of less than 630 ns is recommended for the Financial1 workload, assuming that the SCM write/read latency ratio is 5.

Rectifying pitfalls in the performance evaluation of flash solid-state drives

Today’s data storage systems are increasingly adopting flash-based solid-state drives (SSD), in which new data is written out-of-place. The space occupied by invalidated data is reclaimed by means of a garbage-collection process. This involves additional write operations that result in write amplification, which negatively affects the performance, endurance, and lifetime of SSDs. Several garbage-collection schemes have been proposed in the literature and corresponding models have been developed for assessing their efficiency. We demonstrate that some of these publications arrive at conflicting results. We establish that the discrepancies identified are due to pitfalls in the modeling and analysis of some of the basic garbage-collection schemes. We effectively resolve these discrepancies by rectifying the pitfalls and developing proper analytical models that yield accurate results. We obtain new results for the circular scheme that are subsequently used to develop a new accurate model for the windowed greedy garbage-collection scheme. Results of theoretical and practical importance are analytically derived and experimentally confirmed. They demonstrate that, as the window size decreases, the write amplification increases, illustrating the tradeoff between computation time and write amplification. The results also show that, under certain conditions, the write amplification of the simple circular scheme can be similar to that of the optimum, albeit more complex greedy garbage-collection scheme. In this case, the write amplification for the windowed greedy scheme is essentially found to be independent of the window size.

Design of Remote Destruction SSD

An implementation of a remote destruction solid state drive (SSD) was introduced in the design. The advanced technology of rapid data destruction, the technology of breakdown the flash with high-voltage pulse and the technology of GSM is combined together. As a result, user can operate through a simple command (text message or a call) to destroy all data in SSD, as long as the user confirms SSD is out of control. The method of erasing data and destroying the flash I/O are both executed, so the data can’t be recovered after destruction. At last, some tests are displayed to verify the performance of the remote destruction SSD.

PASS: a simple, efficient parallelism-aware solid state drive I/O scheduler

Emerging non-volatile memory technologies, especially flash-based solid state drives (SSDs), have increasingly been adopted in the storage stack. They provide numerous advantages over traditional mechanically rotating hard disk drives (HDDs) and have a tendency to replace HDDs. Due to the long existence of HDDs as primary building blocks for storage systems, however, much of the system software has been specially designed for HDD and may not be optimal for non-volatile memory media. Therefore, in order to realistically leverage its superior raw performance to the maximum, the existing upper layer software has to be re-evaluated or re-designed. To this end, in this paper, we propose PASS, an optimized I/O scheduler at the Linux block layer to accommodate the changing trend of underlying storage devices toward flash-based SSDs. PASS takes the rich internal parallelism in SSDs into account when dispatching requests to the device driver in order to achieve high performance. Specifically, it partitions the logical storage space into fixed-size regions (preferably the component package sizes) as scheduling units. These scheduling units are serviced in a round-robin manner and for every chance that the chosen dispatching unit issues only a batch of either read or write requests to suppress the excessive mutual interference. Additionally, the requests are sorted according to their visiting addresses while waiting in the dispatching queues to exploit high sequential performance of SSD. The experimental results with a variety of workloads have shown that PASS outperforms the four Linux off-the-shelf I/O schedulers by a degree of 3% up to 41%, while at the same time it improves the lifetime significantly, due to reducing the internal write amplification.