Performance Of Power MOSFETs Research Articles

A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels

This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design.

Small-Signal Impedance and Split C-V Characterization of High-κ SiC Power MOSFETs

In this work, the improvement of SiC power MOSFET performance achieved using high-κ gate-dielectrics instead of the standard SiO2 is investigated by means of advanced gate-impedance characterization. The benefit of using high-κ gate-dielectrics with high dielectric constant is demonstrated by comparing SiC MOSFETs with pure high-κ, a stack of SiO2/high-κ, as well as pure SiO2. Namely, the fabricated high-κ SiC MOSFETs show a superior performance to commercial SiC MOSFETs with SiO2/SiC interface with respect to channel resistance and interface quality. The proposed characterization approach is non-destructive and applicable to packaged power devices.

COMPARATIVE ANALYSIS OF THERMAL STRESS OF Si AND SiC MOSFETs

The performance of power MOSFET is affected by high thermal stress exposure. A high level of thermal stress is induced when the MOSFET experiences a temperature change. This finding is about the bonding wire lift-off on the solder pad. The MOSFET model is designed with the heatsink to ensure accurate results are obtained in this research work. The key intention of this research is to investigate the condition of silicon and silicon carbide power MOSFETs during thermal stress. The thermal properties of silicon and silicon carbide MOSFET were investigated by developing a 3D modal and thermal stress simulation in the COMSOL Multiphysics software. Thermal resistance was calculated by randomly selecting a power loss value of 100 Watts. Junction temperature for silicon and silicon carbide MOSFET was taken from several articles mentioned in the results and discussion.
 Keywords: Thermal stress, bonding wire lift-off, temperature change, MOSFET

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Abstract Silicon-Carbide (SiC) device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon (Si) counterpart, SiC offers a greater possibility for high powered switching applications in extreme environment. In particular, SiC Metal-Oxide-Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing SiC power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Evaluation of Lateral Power MOSFETs in a Synchronous Buck Converter Using a Mixed-Mode Device and Circuit Simulation

This paper presents an evaluation of laterally double-diffused MOS transistors in synchronous dc-dc buck converters using a physical-based mixed device and circuit simulation. It is observed that impact ionization of the low-side transistor can be very high after the dead-time drain overshoot voltage point. In addition, heavy ion irradiation degrades power MOSFET performance and may lead to a potential circuit malfunction due to a significant increase in transient current if heavy ions strike the dc-dc buck converter at a critical time during switching.

CAD tools to optimize power MOSFET performance using channel reverse conduction

In this paper, a contribution to the characterization of power MOS transistors under optimized switching behavior is presented. This behavior is shown to be appropriate for improving the performance of new high frequency power processing topologies. Reverse conduction through the channel resistance is imposed, thus avoiding the problem of integral diode recovery time without resorting to external diodes. Control circuit design is discussed. Advantages and drawbacks are analyzed and tested in a series resonant converter. An insight into MOSFET reverse conduction modeling is presented, aimed at the development of an accurate model for computer aided design of topologies using the MOSFET's bidirectional paths. Simulation results are shown to prove the accuracy of the model. >

Switching performance of power MOSFETs with capacitive loads at high frequency and high voltage for square wave generators

The limitations of switching capacitive loads between high voltages (1000 V or more) and at high frequencies (10 MHz) using power MOSFETs are discussed. For practical designs, despite the fast rise times of MOSFETs (25 ns), the upper frequency of operation for a specified capacitance and voltage depends mainly on the thermal resistance of the MOSFET. Equations and graphs are presented to show the compromise between load capacitance, required frequency and applied voltage.

High frequency switching of power MOSFETs

The effect of the source terminal parasitic inductance on the switching performance of power MOSFETs has been investigated. Results are given of the improvement in switching times produced when an IRF450 in a T03 package is modified to include a second source lead for drive purposes.

High-performance MOSFET—A correspondence

The limiting factors in the performance of power MOSFET's are discussed in response to a previously published paper [1]. The limitations of diffused guard rings, use of SIPOS, R ON and switching response are noted. Calculated R ON and measured data are presented for VMOS and DMOS designs, which indicate the advantage of DMOS.