Performance Of Multiprocessors Research Articles

Considerations regarding the composition of the cockpit view for a modern simulator

This study shows how to generate images and compose images in the modern simulator room by starting multiple work sessions running at the same time so that all active server stations and the station to connect to are continuously displayed. Each server handles specific functions of the simulation process and runs a dedicated software application for its specific functions. For a supervised flight simulator, the following functions need to have dedicated applications: 1) Flight Dynamics Simulation, 2) Graphical projection, 3) Cockpit and Flight instrumentation simulation and integration, 4) Supervisor station. Out of these functions, Graphical projections and Cockpit and Flight instrumentation and integration require the most computational resources. Simulators need to present the view from a cockpit which requires a field of view of at least 180 degrees. This requires at least three displays usually in the form of projectors. In legacy implementations due to computational bottlenecks, each projector needed a dedicated computer. Similarly, the Cockpit and Flight instrumentation simulation requires usually upwards of 100 flight instrument simulations and embedded processors to be managed. In legacy implementations, one computer is needed for each piloting station. In recent implementations due to the increased performance of multi-core processors, many of these functions can be handled by single computers: the flight dynamics simulation and graphical projection functions can currently be handled by a single computer, similarly, all Cockpit and Flight instrumentation simulation and integration can be handled by another computer. Thus, a minimum of three servers are required to ensure full functionality of supervised simulation using modern computing systems.

Performance aware shared memory hierarchy model for multicore processors

Despite the fact that multicore processors have a better instruction execution speed and lower power consumption, they also encounter a set of design challenges. The appearance of multicore and many core architectures has raised the problem of managing shared hierarchical memory systems. The main focus of this paper is to evaluate the behavior of shared hierarchical memory systems by modeling their response time analytically. Since the gap between the memory and processor speed increases rapidly, it gets more crucial to find an analytical model that includes the significant factors that affect the performance of hierarchical memory systems. The proposed model considers the interdependence between different memory layers and differentiates between the memory response time and memory system time. Moreover, the model evaluates the effect of memory hierarchy on the variance of the memory access time. The existence of a large variance can lead to extremely long wait queues which can dramatically affect the performance of multicore processors

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of the hottest server components (i.e., cores and cache). Previous methods focused on either improving energy efficiency by adopting new hybrid-cache architectures including the resistive random-access memory (RRAM) and static random-access memory (SRAM) at the hardware level, or exploring tradeoffs between lifetime limitation and performance of multicore processors under stable workloads conditions. Therefore, no work has so far proposed a co-optimization method with hybrid-cache-based server architectures for real-life dynamic scenarios taking into account scalability, performance, lifetime reliability, and energy efficiency at the same time. In this article, we first formulate a reliability model for the hybrid-cache architecture to enable precise lifetime reliability management and energy efficiency optimization. We also include the performance and energy overheads of cache switching, and optimize the benefits of hybrid-cache usage for better energy efficiency and performance. Then, we propose a runtime <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> -learning-based reliability management and performance optimization approach for multicore microprocessors with the hybrid-cache architecture, jointly incorporated with a dynamic preemptive priority queue management method to improve the overall tasks’ performance by targeting to respect their end time limits. Experimental results show that our proposed method achieves up to 44% average performance (i.e., tasks execution time) improvement, while maintaining the whole system design lifetime longer than five years, when compared to the latest state-of-the-art energy efficiency optimization and reliability management methods for computing servers.

VecDualSPHysics: A vectorized implementation of Smoothed Particle Hydrodynamics method for simulating fluid flows on multi-core processors

As one of the most promising mesh-free numerical approaches, the Smoothed Particle Hydrodynamics (SPH) algorithm can be used for simulating many engineering problems. However, it is necessary to fully exploit the performance of computing processors for realizing extremely large-scale parallel simulations. In this paper, we focused on maximizing the performance of a SPH program by vectorizing on modern multi-core processors. We summarize the general principles of vectorization including the branch vectorization, vector reduction and instruction set optimization approaches. Then, a vectorized version VecDualSPHysics was implemented based on these basic vectorization principles. Experiments show that VecDualSPHysics has a significant performance improvement over the original DualSPHysics. By using AVX2 instruction set combined with OpenMP, we obtained up to 4.3x speedups on a single multi-core processor, and the maximal speedup is 6.3x for AVX-512 instruction set, which is much faster than the pure OpenMP-based multi-threading version. The VecDualSPHysics shows the great potential of exploiting the performance of multi-core processors by vectorization and can further be used to optimize the massively parallel SPH simulations.

COCKTAIL: Multicore Co-Optimization Framework With Proactive Reliability Management

High performance computing (HPC) servers aim to meet an increase in the number and complexity of tasks and, consequently, to address the energy efficiency challenge. In addition to energy efficiency, it is essential to manage lifetime limitations of power-hungry components of servers (e.g., cores and cache), hence avoiding server failure before its lifetime period. Traditional approaches focus on either using hybrid caches to reduce the leakage power of traditional static random-access memory (SRAM) cache, and thus increase the energy efficiency, or the trade-off between the lifetime and performance of multi-core processors. However, these approaches fall short in terms of flexibility and applicability for HPC tasks in terms of multi-parametric optimization including quality-of-service (QoS), lifetime reliability, and energy efficiency. As a result, in this paper we propose COCKTAIL, a holistic strategy framework to jointly optimize the energy efficiency of multi-core server processors and tasks performance in the HPC context, while guaranteeing the lifetime reliability. First, we analyze the best cache technology among traditional SRAM and resistive random access memory (RRAM), within the context of hybrid cache architectures, to improve the energy efficiency and manage cache endurance limits with respect to tasks requirements. Second, we introduce a novel efficient proactive queue optimization policy to reorder HPC tasks for execution considering their end time and possible reliability effects on the use of the hybrid caches. Third, we present a dynamic model predictive control (MPC)-based reliability management method to maximize task performance, by controlling the frequency, temperature, and target lifetime of the server processor. Our results demonstrate that, while consuming similar energy, COCKTAIL provides up to 60% QoS improvement when compared to latest state-of-the-art energy optimization and reliability management techniques in the HPC context. Moreover, our strategy guarantees a design lifetime longer than 5 years for the whole HPC system.

Loop Selection for Multilevel Nested Loops Using a Genetic Algorithm

Loop selection for multilevel nested loops is a very difficult problem, for which solutions through the underlying hardware-based loop selection techniques and the traditional software-based static compilation techniques are ineffective. A genetic algorithm- (GA-) based method is proposed in this study to solve this problem. First, the formal specification and mathematical model of the loop selection problem are presented; then, the overall framework for the GA to solve the problem is designed based on the mathematical model; finally, we provide the chromosome representation method and fitness function calculation method, the initial population generation algorithm and chromosome improvement methods, the specific implementation methods of genetic operators (crossover, mutation, and selection), the offspring population generation method, and the GA stopping criterion during the GA operation process. Experimental tests with the SPEC2006 and NPB3.3.1 standard test sets were performed on the Sunway TaihuLight supercomputer. The test results indicated that the proposed method can achieve a speedup improvement that is superior to that by the current mainstream methods, which confirm the effectiveness of the proposed method. Solving the loop selection problem of multilevel nested loops is of great practical significance for exploiting the parallelism of general scientific computing programs and for giving full play to the performance of multicore processors.

CellS: A Cell-Inspired Efficient Software Framework for AI-Enabled Application on Resources-Constrained Mobile System

Today’s mobile processors generally have multiple cores and sufficient hardware resources to support AI-enabled software operation. However, very few AI applications make full use of the computing performance of mobile multiprocessors. This is because the typical software development is sequential, and the degree of parallelism of the program is very low. In the increasingly complex AI-driven and software development projects with natural human–computer interaction, this will undoubtedly cause a waste of mobile computing resources that are originally limited. This paper proposes an intelligent system software framework, CellS, to improve smart software development on multicore mobile processor systems. This software framework mimics the cell system. In this framework, each cell can autonomously aware changes in the environment (input) and reaction (output) and may change the behavior of other cells. Smart software can be regarded as a large number of cells interacting with each other. Software developed based on the CellS framework has a high degree of scalability and flexibility and can more fully use multicore computing resources to achieve higher computing efficiency.

Hotspot thermal management in microchannel heat sinks with vortex generators

Vortex generators (VGs) have been widely applied in the microchannel heat sinks to improve the thermal-hydraulic performance in multicore processors. However, most studies focus on global heat transfer enhancement of microchannel, while the hotspot temperature is often neglected. In this paper, a numerical study of hotspot-targeted thermal management using VGs is performed in a rectangular microchannel with a heat flux of 400 W/cm2 and 50 W/cm2 respectively at the hotspot and background region. With the maximum thermal resistance, pumping power and the overall performance factor as the key metrics, the performances of VGs in four configurations (co-flow-up, co-flow-down, counter-flow-up and counter-flow-down) are compared with a smooth microchannel without VG. Deionized water with temperature-dependent thermo-physical properties is used as the coolant with the Re in the range of 66–330. The results indicate that the adoption of VGs can significantly improve the cooling effect over the hotspot with a lower pressure loss penalty comparing with the smooth microchannel. In addition, the VGs in a “co-flow” configuration lead to the fluid circulation effect and transport the coolant in the core region of the microchannel to the sidewalls. It is also noted that comparing with the smooth microchannel, more than 78.8% pumping power can be saved by using the “co-flow-down” configuration to achieve the same cooling effect to maintain the average temperature at 304.7 K over the hotspot. Geometric parameter analysis reveals that the increase in the height and attack angle of VGs results in more pressure loss, whereas the enhanced heat transfer is insignificant when the VG's height ratio exceeds 0.2 or the attack angle surpasses 45°. Taking full account of the heat transfer performance and pressure loss, VGs with a height ratio of 0.2 and attack angle of 45° are recommended for practical applications.

Investigating Policies for Performance of Multi-core Processors

Investigating Policies for Performance of Multi-core Processors

Dynamic Data Allocation and Task Scheduling on Multiprocessor Systems With NVM-Based SPM

Low-power and short-latency memory access is critical to the performance of chip multiprocessor (CMP) system devices, especially to bridge the performance gap between memory and CPU. Together with increased demand for low-energy consumption and high-speed memory, scratch-pad memory (SPM) has been widely adopted in multiprocessor systems. In this paper, we employ a hybrid SPM, composed of a static random-access memory and a nonvolatile memory (NVM), to replace the cache in CMP. However, there are several challenges related to the CMP that need to be addressed, including how to dynamically assign processors to application tasks and dynamically allocate data to memories. To solve these problems based on this architecture, we propose a novel dynamic data allocation and task scheduling algorithm, i.e., dynamic greedy data allocation and task scheduling (DGDATS). Experiments on DSP benchmarks demonstrate the effectiveness and efficiency of our proposed algorithms; namely, our proposed algorithm can generate a highly efficient dynamic data allocation and task scheduling approach to minimize the total execution cost and produce the least amount of write operations on NVMs. Our extensive simulation study demonstrates that our proposed algorithm exhibits an excellent performance compared with the heuristic allocation (HA) and adaptive genetic algorithm for data allocation (AGADA) algorithms. Based on the CMP systems with hybrid SPMs, DGDATS reduces the total execution cost by 22.18% and 51.37% compared with those of the HA and AGADA algorithms, respectively. Additionally, the average number of write operations on NVM is 19.82% lower than that of HA.

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

The exponentially increasing performance of chip multiprocessors (CMPs) predicted by Moore's Law is no longer due to the increasing clock rate of a single CPU core, but on account of the increase of core counts in the CMP. More transistors are integrated within the same footprint area as the technology node shrinks to deliver higher performance. However, this is accompanied by higher power dissipation that usually exceeds the coping capability of inexpensive cooling techniques. This Power Wall prevents the chip from running at full speed with all the devices powered-on. This is known as the dark silicon problem. Another major bottleneck in CMP development is the imbalance between the CPU clock rate and memory access speed. This Memory Wall keeps the CPU from fully utilizing its compute power. To address both the Power and Memory Walls, we propose a monolithic 3D hybrid architecture that consists of a multi-core CPU tier, a fine-grain dynamically reconfigurable (FDR) field-programmable gate array (FPGA) tier, and multiple resistive RAM (RRAM) tiers. The FDR tier is used as an accelerator. It uses the concept of temporal logic folding to localize on-chip communication. The RRAM tiers are connected to the CPU and FDR tiers through an efficient memory interface that takes advantage of the tremendous bandwidth available from monolithic inter-tier vias and hides the latency of large data transfers. We evaluate the architecture on two types of benchmarks: compute-intensive and memory-intensive. We show that the architecture reduces both power and energy significantly at a better performance for both types of applications. Compared to the baseline, our architecture achieves an average of 43.1× and 2.5× speedup on compute-intensive and memory-intensive benchmarks, respectively. The power and energy consumption are reduced by 5.0× and 40.5×, respectively, for compute-intensive applications, and 2.0× and 4.2×, respectively, for memory-intensive applications. This translates to 1745.3× energy-delay product (EDP) improvement for compute-intensive applications and 10.5× for memory-intensive applications.

A load-balanced congestion-aware routing algorithm based on time interval in wireless network-on-chip

Network-on-chip (NoC) has been introduced to increase the performance of chip multiprocessors (CMPs) and execute parallel programs. Although NoC is known as a modular and scalable infrastructure for interconnections, there are still some challenges with conventional NoC such as high latency and power consumption due to the communication among long-distance (LD) cores. In this regard, wireless network-on-chip (WiNoC) is a potential solution that can provide high bandwidth and low latency by means of the unique features of wireless interconnects. However, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and shared use of these channels by all processing elements (PEs). In this study, a load-balanced time-based congestion-aware (LTCA) routing algorithm is proposed to eliminate the congestion of WRs and distribute the traffic load on the wired and wireless networks in a balanced way. LTCA is a deadlock-free routing algorithm in which only a limited number of packets are allowed to use wireless channels. The required time for transmitting the selected packets through wireless links is measured with regard to the bandwidth of the wireless channels and traffic load. Simulation results on synthetic traffic patterns and real-world 3-tuple traffic patterns indicated a considerable improvement in latency, throughput, wired and wireless link utilization and packet loss probability.

Feedback-Based Admission Control for Firm Real-Time Task Allocation with Dynamic Voltage and Frequency Scaling

Feedback-based mechanisms can be employed to monitor the performance of Multiprocessor Systems-on-Chips (MPSoCs) and steer the task execution even if the exact knowledge of the workload is unknown a priori. In particular, traditional proportional-integral controllers can be used with firm real-time tasks to either admit them to the processing cores or reject in order not to violate the timeliness of the already admitted tasks. During periods with a lower computational power demand, dynamic voltage and frequency scaling (DVFS) can be used to reduce the dissipation of energy in the cores while still not violating the tasks&rsquo; time constraints. Depending on the workload pattern and weight, platform size and the granularity of DVFS, energy savings can reach even 60% at the cost of a slight performance degradation.

Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs

Nanophotonics is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features, which can be useful for performance and energy in future Chip Multi-Processors (CMPs). This article proposes a novel arbitrated all-optical path-setup scheme for tiled CMPs adopting circuit-switched optical networks. It aims at significantly reducing path-setup latency and overall energy consumption. The proposed arbitrated scheme is able to configure multiple photonic switches simultaneously, instead of sequentially as it is done in state-of-the-art proposals. The proposed fast optical path-setup solution reduces the overhead in each transmission and, most importantly, allows optical circuit-switched networks to effectively serve cache coherence traffic, which is mainly composed of relatively small messages. Specifically, we propose a single-arbiter scheme where the whole topology is managed by a central module (single-arbiter) that takes care of the path-setup procedures. Then, to tackle scalability, we propose a logically clustered architecture (multi-arbiter) in which an arbiter is allocated in each logical core-cluster and an ad hoc distributed reservation protocol coordinates arbiters to manage inter-cluster path reservations. We show that our proposed single-arbiter architecture outperforms a state-of-the-art optical network with sequential path-setup (optical baseline) in the case of 8- and 16-core tiled CMP setups. However, due to serialization issues, the single-arbiter solution is not able to compete with a reference electronic baseline for bigger 32- and 64-core setups even if still performing much better than the optical baseline. Conversely, our multi-arbiter hierarchical solution allows us to improve performance up to almost 20% and 40% for 32- and 64-core setups, respectively, demonstrating a wide applicability of the proposed technique. Energy-wise, the analyzed solutions enable significant savings compared to both the optical baseline with sequential path setup, and to the electronic counterpart. Specifically, results show more than 25% average improvement for the single-arbiter in the 8- and 16-core cases, and more than 40% and 15% savings for the multi-arbiter in the 32- and 64-core cases, respectively.

A Novel Methodology on Optimizing the Performance of Multi-core Processor Using FPGA

With rapid progress in microelectronic technology and higher performance requirements, multi-core processors (MP) have become widely used in various applications. Among them, multiprocessor System-on-Chip (MPSoC) received focus because of its high integration level and low power solution. This work proposed more efficient way to implement MPSoC with higher performance. Synchronous data flow (SDF) is used to model high-speed MPSoC systems, and to simulate the system level functional algorithms. After building a suitable FPGA platform architecture, we prototype these SDF graphs onto FPGA based MPSoC platform. Simulation results show that the MPSoC platform has higher performance than a single processor platform, with novel architecture and scheduling strategy used. Furthermore, different scheduling strategies, including static order and run-time order, are compared on MPSoC. The results have shown that the optimized static order strategy can achieve higher performance than run-time order strategy, with less buffer cost.

Design and Evaluation of Binary-Tree Based Scalable 2D and 3D Network-on-Chip Architecture

Network-on-Chip (NoC) has been developed as a most prevailing innovation in the paradigm of communication-centric technology. It solves the limitations of bus-based systems, with the incorporation of 3D IC technology, and it reduces packaging density and improves performance of Multiprocessor System-on-Chip. There is need of suitable NoC topology for these applications and desired performances. This paper proposes a scalable binary tree-based topology for 2D and 3D NoCs. The average degree of the proposed network is reduced around 40% of the torus whereas the diameter also reduced significantly, as compared to other topologies.

멀티코어 프로세서의 성능에 대한 DRAM의 영향

멀티코어 프로세서의 성능에 대한 DRAM의 영향

Noc-HMP

Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

Multi-core versus many-core computing for many-task Branch-and-Bound applied to big optimization problems

On the road to exascale, coprocessors are increasingly becoming key building blocks of High Performance Computing platforms. In addition to their energy efficiency, these many-core devices boost the performance of multi-core processors. In this paper, we revisit the design and implementation of Branch-and-Bound (B&B) algorithms for multi-core processors and Intel Xeon Phi coprocessors considering the offload mode as well as the native one. In addition, two major parallel models are considered: the master–worker and the work pool models. We address several parallel computing issues including processor–coprocessor data transfer optimization and vectorization. The proposed approaches have been experimented using the Flow-Shop scheduling problem (FSP) and two hardware configurations equivalent in terms of energy consumption: Intel Xeon E5-2670 processor and Intel Xeon Phi 5110P coprocessor. The reported results show that: (1) the proposed vectorization mechanism reduces the execution time by 55.4% (resp. 30.1%) in the many-core (resp. multi-core) approach ; (2) the offload mode allows a faster execution on MIC than the native mode for most FSP problem instances ; (3) the many-core approach (offload or native) is in average twice faster than the multi-core approach ; (4) the work pool parallel model is more suited for many/multi-core B&B applied to FSP than the master–worker model because of its irregular nature.

A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom

To increase the performance of chip multiprocessors, optical network-on-chip (ONoC) becomes promising because of its high bandwidth and low energy consumption. In this paper, we propose an architecture called RPNoC (Ring-based Packet-switched NoC), which uses few optical devices. Specifically, Single-waveguide RPNoC employs only one waveguide. Multiwaveguide RPNoC introduces space division multiplexing to make the architecture highly scalable. A novel wavelength assignment method and a deadlock-free deterministic routing algorithm are jointly designed, which make the network diameter quite small. This design also guarantees deadlock freedom, a little resource use, and low complexity at the same time. Evaluation is carried out for the 64-node RPNoC under different synthetic and realistic traffic patterns. The simulation result shows that it yields high throughput and low latency. Comparison with other packet-switched ONoCs shows that RPNoC has the lowest energy consumption.