Performance Of Memory Devices Research Articles

Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 103 between the two binary states. Programmed data could be retained for 103 s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.

In Situ Tuning of Magnetization and Magnetoresistance in Fe3O4 Thin Film Achieved with All-Solid-State Redox Device.

An all-solid-state redox device composed of Fe3O4 thin film and Li(+) ion conducting solid electrolyte was fabricated for use in tuning magnetization and magnetoresistance (MR), which are key factors in the creation of high-density magnetic storage devices. Electrical conductivity, magnetization, and MR were reversibly tuned by Li(+) insertion and removal. Tuning of the various Fe3O4 thin film properties was achieved by donation of an electron to the Fe(3+) ions. This technique should lead to the development of spintronics devices based on the reversible switching of magnetization and spin polarization (P). It should also improve the performance of conventional magnetic random access memory (MRAM) devices in which the ON/OFF ratio has been limited to a small value due to a decrease in P near the tunnel barrier.

FTIR studies on polymorphic control of PVDF ultrathin films by heat-controlled spin coater

The performance of organic polymer-based memory devices based on polyvinylidene fluoride (PVDF) ultrathin films depends on the extent of its ferroelectric crystalline phase content. In the present study, the changes in polymorphs of PVDF ultrathin films prepared by using heat-controlled spin coater are examined. The polymorphic changes were analyzed by using FTIR-transmission (TS) and FTIR-grazing incidence reflection–absorption spectroscopy (GIRAS) as a function of varying (i) spin-coating temperatures (SCT-30 to 80 °C), (ii) spin-coating substrates (KBr, ITO and Gold) and (iii) thermal treatments [as-cast (AC) at 30 °C, annealed at 130 °C (AN130) and melt (200 °C)-slow cooled (MSC)] conditions. Compared to MSC samples, the AC and AN130 samples exhibited higher β-crystalline (polar, all-trans) phase along with the complete absence of α-crystalline (non-polar, tgtg′) phase at lower SCT-30 and 40 °C irrespective of the substrates used, thereby avoiding the need of high-temperature SCT conditions. Among the three substrates used, FTIR-GIRAS data obtained using ITO and Gold substrates were more favored than the FTIR-TS data obtained using KBr window due to their real-time usage as the substrate for electronic applications.

Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer.

Impact of Post-Oxide Deposition Annealing on Resistive Switching in HfO<sub>2</sub>-Based Oxide RRAM and Conductive-Bridge RAM Devices

In this letter, we report the impact of post-oxide deposition annealing on the performance of HfO2-based resistive random access memory (RRAM) devices, namely, oxygen-ion-based oxide RRAM (OxRRAM) and Cu-ion-based conductive-bridge RAM (CBRAM) devices. Considerable degradation of the ON/OFF ratio and switching properties was observed in the OxRRAM devices after high-temperature annealing in vacuum, which is attributed to a considerable amount of oxygen vacancies created in the switching layer. However, the substantial improvement in device performance, such as stable switching, high switching cycles, decreased set/reset voltages, and near-100% device yield, were obtained in the CBRAM devices during the post-HfO2 deposition annealing in vacuum.

Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric field control of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultrafast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory merges features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs-based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM, resistive RAM, and spin transfer torque RAM. MeRAM can achieve ultrafast switching (<1 ns), low switching energy (∼1 fJ), and compact cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$6\;F^2$</tex-math></inline-formula> with a shared source region, as well as nonvolatility. For another application, we propose the VCMA-MEJ-based TCAM, which will be referred to as MeTCAM, consisting of 4T-2MEJs. Since MeTCAM fully exploits the low power and high density features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math>$44\;F^2 $</tex-math></inline-formula> ) compared to previous works.

Phase Transformations and Thermal Stability of CdSe Quantum Dots: Cubic to Hexagonal

CdSe quantum dots (QDs) having size 3–5 nm have been synthesized by chemical co-precipitation method in mixed amorphous and cubic phase. These QDs have been characterized by using X-ray diffraction (XRD), high resolution transmission electron microscopy (HRTEM) and Fourier transform infrared (FTIR) spectrometry. Cubic phase is confirmed by XRD and amorphous phase have been found using differential scanning calorimetry (DSC). The thermal analysis carried out by using DSC at different heating rates shows endothermic and exothermic peaks at different temperatures corresponding to their glass transition and different crystalline phases. The cubic phase of the crystalline CdSe obtained at 261 °C in the DSC scan of as prepared sample start transforming to stable hexagonal phase of CdSe corresponding to second crystallization peak 317 °C in DSC thermogram. Differential thermal analysis (DTA) and thermogravimetric analysis (TGA) have also been used to determine the crystallization temperature (257 °C) and weight loss in the temperature range 220–267 °C. Activation energies corresponding to two exothermic peaks (cubic and hexagonal phase) have been determined by employing different theoretical models. Lower activation energy of the hexagonal phase corresponding to second exothermic peak obtained at higher temperature in the DSC thermogram shows the higher thermal stability of this phase and could be employed for preparing a material to improve the performance of memory devices, solar cells etc.

Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory**Project supported by the National Natural Science Foundation of China (Nos. 61474137, 61176073, 61306107).

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

Dynamic Charge Carrier Trapping in Quantum Dot Field Effect Transistors.

Noncrystalline semiconductor materials often exhibit hysteresis in charge transport measurements whose mechanism is largely unknown. Here we study the dynamics of charge injection and transport in PbS quantum dot (QD) monolayers in a field effect transistor (FET). Using Kelvin probe force microscopy, we measured the temporal response of the QDs as the channel material in a FET following step function changes of gate bias. The measurements reveal an exponential decay of mobile carrier density with time constants of 3-5 s for holes and ∼10 s for electrons. An Ohmic behavior, with uniform carrier density, was observed along the channel during the injection and transport processes. These slow, uniform carrier trapping processes are reversible, with time constants that depend critically on the gas environment. We propose that the underlying mechanism is some reversible electrochemical process involving dissociation and diffusion of water and/or oxygen related species. These trapping processes are dynamically activated by the injected charges, in contrast with static electronic traps whose presence is independent of the charge state. Understanding and controlling these processes is important for improving the performance of electronic, optoelectronic, and memory devices based on disordered semiconductors.

Altering the Position of Phenyl Substitution to Adjust Film Morphology and Memory Device Performance.

In this study, two structural isomers α-PBT and β-PBT, which only differ in the phenyl substituent position on the quinoline chromophore, have been designed and successfully synthesized. The influences of substituent position on the film morphology and the storage performance of the devices were investigated. Both molecules employed in the memory devices exhibited same nonvolatile binary (write-once-read-many-times; WORM) characteristics, but the switch threshold voltage (Vth) of the β-PBT-based device was clearly lower than that of the α-PBT-based device. Simulation results demonstrate that the variation of the phenyl substituent position led to different intermolecular stacking styles and thus to varied grain sizes for each film morphology. This work illustrates that altering the phenyl substituent position on the molecular backbone could improve the quality of the film morphology and reduce power consumption, which is good for the rational design of future advanced organic memory devices (OMDs).

A Novel Organic Electrical Memory Device Based on Metallofullerene-Grafted Polymer

Organic memory materials have advantages in flexible, large area film-forming, and low cost compared with inorganic storage materials. Developing new materials with high read-write speed, low-power consumption, multi-value storage capacity and other excellent properties has been a subject for the study of next-generation non-volatile storage devices. Metallofullerenes could be used either as electron acceptor or as electron donor to form charge transfer compound with polymers containing electron withdrawing or electron donor compounds. We successfully used metallofullerene-based polymer to fabricate ITO/Gd@C82-PVK/Al sandwich nonvolatile memory device. The results of I-V test indicated that the new material exhibited typical bistable electrical switching and a nonvolatile rewritable memory effect. The theory calculation indicated that the encaged metal may serve as the important electron trapping center. PVK-Gd@C82 is thus an example of a new type charge-transfer complex that integrates the conventional organic and inorganic charge transfer complexes, which provides a potential method to improve the processing, morphological stability, and electrical performance of organic memory devices.

Regulation of the forming process and the set voltage distribution of unipolar resistance switching in spin-coated CoFe2O4 thin films.

We report the preparation of (111) preferentially oriented CoFe2O4 thin films on Pt(111)/TiO2/SiO2/Si substrates using a spin-coating process. The post-annealing conditions and film thickness were varied for cobalt ferrite (CFO) thin films, and Pt/CFO/Pt structures were prepared to investigate the resistance switching behaviors. Our results showed that resistance switching without a forming process is preferred to obtain less fluctuation in the set voltage, which can be regulated directly from the preparation conditions of the CFO thin films. Therefore, instead of thicker film, CFO thin films deposited by two times spin-coating with a thickness about 100 nm gave stable resistance switching with the most stable set voltage. Since the forming process and the large variation in set voltage have been considered as serious obstacles for the practical application of resistance switching for non-volatile memory devices, our results could provide meaningful insights in improving the performance of ferrite material-based resistance switching memory devices.

Effect of Pulse and dc Formation on the Performance of One-Transistor and One-Resistor Resistance Random Access Memory Devices

We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor (1T1R) resistance random access memory (RRAM) device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state (HRS) under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament (CF) formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state (LRS) can be easily changed by removing a few trapping states from the conducting path. Hence, a higher HRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.

Conjugated Polymer Nanoparticles as Nano Floating Gate Electrets for High Performance Nonvolatile Organic Transistor Memory Devices

A molecular nano‐floating gate (NFG) of pentacene‐based transistor memory devices is developed using conjugated polymer nanoparticles (CPN) as the discrete trapping sites embedded in an insulating polymer, poly (methacrylic acid) (PMAA). The nanoparticles of polyfluorene (PF) and poly(fluorene‐alt‐benzo[2,1,3]thiadiazole (PFBT) with average diameters of around 50–70 nm are used as charge‐trapping sites, while hydrophilic PMAA serves as a matrix and a tunneling layer. By inserting PF nanoparticles as the floating gate, the transistor memory device reveals a controllable threshold voltage shift, indicating effectively electron‐trapping by the PF CPN. The electron‐storage capability can be further improved using the PFBT‐based NFG since their lower unoccupied molecular orbital level is beneficial for stabilization of the trapped charges, leading a large memory window (35 V), retention time longer than 104 s with a high ON/OFF ratio of &gt;104. In addition, the memory device performance using conjugated polymer nanoparticle NFG is much higher than that of the corresponding polymer blend thin films of PF/polystyrene. It suggests that the discrete polymer nanoparticles can be effectively covered by the tunneling layer, PMAA, to achieve the superior memory characteristics.

Hierarchically built gold nanoparticle supercluster arrays as charge storage centers for enhancing the performance of flash memory devices.

Flash memory devices with high-performance levels exhibiting high charge storage capacity, good charge retention, and high write/erase speeds with lower operating voltages are widely in demand. In this direction, we demonstrate hierarchical self-assembly of gold nanoparticles based on block copolymer templates as a promising route to engineer nanoparticle assemblies with high nanoparticle densities for application in nanocrystal flash memories. The hierarchical self-assembly process allows systematic multiplication of nanoparticle densities with minimal increase in footprint, thereby increasing the charge storage density without an increase in operating voltage. The protocol involves creation of a parent template composed of gold nanoclusters that guides the self-assembly of diblock copolymer reverse micelles which in turn directs electrostatic assembly of gold nanoparticles resulting in a three-level hierarchical system. Capacitance-voltage (C-V) measurements of the hierarchical nanopatterns with a metal-insulator-semiconductor capacitor configuration reveal promising enhancement in memory window as compared to nonhierarchical nanoparticle controls. Capacitance-time (C-t) measurements show that over half the stored charges were retained when extrapolated to 10 years. The fabrication route can be readily extended to programmed density multiplication of features made of other potential charge storage materials such as platinum, palladium, or hybrid metal/metal oxides for next generation, solution-processable flash memory devices.

Effect of single atom substitution in benzochalcogendiazole acceptors on the performance of ternary memory devices

Ternary memory storage performances of three benzochalcogendiazole derivative based devices clearly demonstrate the effect of single atom substitution on the molecular planarity, film morphologies and device threshold voltages.

N-type chalcogenides by ion implantation.

Carrier-type reversal to enable the formation of semiconductor p-n junctions is a prerequisite for many electronic applications. Chalcogenide glasses are p-type semiconductors and their applications have been limited by the extraordinary difficulty in obtaining n-type conductivity. The ability to form chalcogenide glass p-n junctions could improve the performance of phase-change memory and thermoelectric devices and allow the direct electronic control of nonlinear optical devices. Previously, carrier-type reversal has been restricted to the GeCh (Ch=S, Se, Te) family of glasses, with very high Bi or Pb 'doping' concentrations (~5-11 at.%), incorporated during high-temperature glass melting. Here we report the first n-type doping of chalcogenide glasses by ion implantation of Bi into GeTe and GaLaSO amorphous films, demonstrating rectification and photocurrent in a Bi-implanted GaLaSO device. The electrical doping effect of Bi is observed at a 100 times lower concentration than for Bi melt-doped GeCh glasses.

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

The memory structures Pt/Al2O3/(TiO2)x(Al2O3)1−x/Al2O3/p-Si(nominal composition x = 0.05, 0.50 and 0.70) were fabricated by using rf-magnetron sputtering and atomic layer deposition techniques, in which the dielectric constant and the bottom of the conduction band of the high-k composite (TiO2)x(Al2O3)1−x were adjusted by controlling the partial composition of Al2O3. With the largest dielectric constant and the lowest deviation from the bottom of the conduction band of Si, (TiO2)0.7(Al2O3)0.3 memory devices show the largest memory window of 7.54 V, the fast programming/erasing speed and excellent endurance and retention characteristics, which were ascribed to the special structural design, proper combination of dielectric constant and band alignment in the high-k composite (TiO2)0.7(Al2O3)0.3.

Characteristics of phase transition in boron‐implanted Ge2Sb2Te5 thin films for phase change memory applications

Phase change memory has been considered as one of the most promising alternatives for next‐generation nonvolatile semiconductor memory. Modification of phase change materials by impurity doping has been proved to be an effective way to improve phase change memory device performance. In this study, the most common phase change material, Ge2Sb2Te5 (GST), was employed, and its intrinsic properties were modified using boron–ion implantation. The GST films were implanted with 20 keV boron ions to fluences of 5 × 1014 and 5 × 1015 ions/cm2. The characteristics of the virgin and boron‐implanted GST films were investigated by SIMS, XRD, and in situ resistance measurement. The kinetics of the thermally activated phase transition was also analyzed on the basis of the Arrhenius relationship. The results revealed that both crystallization temperature and activation energy of crystallization increase with increasing the boron fluence. The data retention capability is also enhanced from 83 to 88 °C, corresponding to a criterion of 10‐year archival lifetime. In addition, the XRD spectra indicated that high‐fluence boron–ion implantation partially inhibits the transition of the GST films from face‐centered cubic phase to hexagonal close‐packed phase. In conclusion, the thermal stability of the GST films can be improved through boron–ion implantation. Copyright © 2014 John Wiley &amp; Sons, Ltd.