Performance Of Flash Memory Research Articles

FAST :플래시 메모리 FTL을 위한 완전연관섹터변환에 기반한 로그 버퍼 기법

플래시 메모리가 개인 정보 도구, 유비쿼터스 컴퓨팅 환경, 모바일 제품, 가전 제품 등에 급속한 속도로 활용되고 있다. 플래시 메모리는, 이러한 환경에 저장매체로서 사용되기에 적합한 성질들 - 즉 저전력, 비휘발성, 고성능, 물리적인 안정성, 그리고 휴대성 등 - 을 갖고 있다. 그런데 하드디스크와 달리, 이미 데이터가 기록된 블록에 대해 덮어쓰기가 되지 않는다는 약점을 갖고 있다. 덮어쓰기를 위해서는 해당 블록을 지우고 쓰기 작업을 수행해야 한다. 이와 같은 성질은 플래시 메모리의 쓰기 성능을 매우 저하시킬 수 있다. 이와 같은 문제점을 해결하기 위해 플래시 메모리에는 FTL(Flash Translation Layer)라는 시스템 소프트웨어 모듈을 갖고 있다. 현재까지 많은 FTL 기법들이 제안되었는데, 그 중에서 대표적인 기법으로 로그블록 기법이 있다. 이 기법은 한정된 수의 로그블록을 쓰기 버퍼로 이용함으로써 쓰기에 따른 소거 연산을 줄임으로써 성능을 높인다. 그런데 이 기법은 로그블록의 활용률이 낮다는 것이 단점이다. 이러한 단점은 각 로그블록에 쓰여질 수 있는 섹터들이 블록 단위로 연관(Block Associative Sector Translation - BAST)되기 때문이다. 본 논문에서는 한정된 수의 로그블록들의 활용률을 높이기 위해 임의쓰기(random overwrite) 패턴을 보이는 섹터들을 전체 로그블록들에 완전 연관(Fully Associative Sector Translation - FAST)시킴으로써 활용률을 높이는 FAST 기법을 제안한다. 본 논문의 기여사항을 다음과 같다. 1) BAST 기법의 단점과 그 이유를 밝히고, 2) FAST 기법의 동기, 기본 개념, 그리고 동작원리를 설명하고, 3) 성능평가를 통해 FAST 기법의 우수성을 보인다. Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

Multi-dot floating-gates for nonvolatile semiconductor memories: Their ion beam synthesis and morphology

Scalability and performance of current flash memories can be improved substantially by replacing the floating polycrystalline-silicon gate by a layer of Si dots. Here, we present both experimental and theoretical studies on ion beam synthesis of multi-dot layers consisting of Si nanocrystals (NCs) embedded in the gate oxide. Former studies have suffered from the weak Z contrast between Si and SiO2 in transmission electron microscopy (TEM). This letter maps Si plasmon losses with a scanning TEM equipped with a parallel electron energy loss spectroscopy system. Kinetic Monte Carlo simulations of Si phase separation have been performed and compared with Si plasmon maps. Predicted and measured Si morphologies agree remarkably well, both change with increasing ion fluence from isolated NCs to spinodal pattern. However, the predicted fluences are lower than the experimental ones. We identify as the main reason of this discrepancy the partial oxidation of implanted Si by atmospheric humidity, which penetrates into the as-implanted SiO2.

Multi-Dot Floating-Gates in MOSFETs for Nonvolatile Memories – Their Ion Beam Synthesis and Morphology

ABSTRACTScalability and performance of current flash memories can be improved substantially by novel devices based on Multi-Dot Floating Gate MOSFETs. The multi-dot layer in the very thin gate oxide can be fabricated CMOS-compatibly by ion beam synthesis (IBS). Here, we present both experimental and theoretical studies on IBS of multi-dot layers consisting of Si nanocrystals (NCs). The NCs are produced by ultra low energy Si+ ion implantation, which causes a high Si supersaturation in the shallow implantation region. During post-implantation annealing, this supersaturation leads to phase separation of the excess Si from the SiO2. Till now, the study of this phase separation suffered from the weak z contrast between Si and SiO2 phases in Transmission Electron Microscopy (TEM). Here, this imaging problem is solved by Energy Filtered Scanning Transmission Electron Microscopy (EFSTEM). Additionally, kinetic lattice Monte Carlo simulations of Si phase separation have been performed and compared with EFSTEM images. It has been predicted theoretically that the morphology of the multi-dot Si floating gate changes with increasing ion fluence from isolated, spherical NCs to percolated spinodal Si pattern. These patterns agree remarkably with EFSTEM images. However, the predicted fluence for spinodal pattern is lower than the experimental one. Because oxidants of the ambient atmosphere penetrate into the as-implanted SiO2, a substantial fraction of the implanted Si is lost due to oxidation.

Using data clustering to improve cleaning performance for flash memory

Using data clustering to improve cleaning performance for flash memory

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories. >