Performance Of Field-effect Transistors Research Articles

The Effect оf Laser Radiation оn Functional Properties of MOS Structures

The electrophysical properties of instrument MOSFET structures (capacitor, field-effect transistor with an isolated gate and an induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. Static and dynamic characteristics were measured. The theoretical study was carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristic of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of the structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, the photovoltaic effect in p—n junctions, the photo-Dember effect and tunneling of charge carriers through a gate dielectric. The results of the work are of interest from the point of view of creating high-speed transistors and integrated circuits of a new type.

Exchange-enhanced spin-orbit splitting and its density dependence for electrons in monolayer transition metal dichalcogenides

We show that spin-orbit splitting (SOS) in monolayers of semiconducting transition metal dichalcogenides (TMDs) is substantially enhanced by an electron-electron interaction. This effect, similar to the exchange enhancement of the electron g factor, is most pronounced for conduction band electrons (in particular, in MoS2), and it has a nonmonotonic dependence on the carrier sheet density n. That is, the SOS enhancement is peaked at the onset of filling of the higher-energy spin-split band by electrons, n*, which also separates the regimes of slow (at n<n*) and fast (for n>n*) spin and valley relaxation of charge carriers. Moreover, this density itself is determined by the enhanced SOS value, making the account of exchange renormalization important for the analysis of the spintronic performance of field-effect transistors based on two-dimensional TMDs. Published by the American Physical Society 2024

Thermal, mechanical, and electrical properties of Si-stacked nanosheet transistors using machine learning interatomic potentials

Thermal and mechanical properties play a key role in optimizing the performance of nanoelectronic devices. In this study, the lattice thermal conductivity (κL) and elastic constants of Si nanosheets at different sheet thicknesses were determined using recently developed machine learning interatomic potentials (MLIPs). A Si nanosheet with a minimum thickness of 10 atomic layers was used for model training to predict the properties of sheets with greater thicknesses. The training dataset was efficiently constructed using stochastic sampling of the potential energy surface (PES). Density functional theory (DFT) calculations were used to extract
the MLIP, which served as the basis for further analysis. The Moment Tensor Potential (MTP) method was used to obtain the MLIP in this study. The results showed that, at sub-6 nm sheet thickness, the thermal conductivity dropped to ∼ 7 % of its bulk value, whereas some stiffness tensor components dropped to ∼ 3 % of the bulk values. These findings contribute to the understanding of heat transport and mechanical behavior of ultrathin Si nanosheets, which is crucial for designing and optimizing nanoelectronic devices. The technological implications of the extracted parameters on nanosheet field-effect transistor (NS-FET) performance at advanced technology nodes were evaluated using TCAD device simulations.

Simulation Study on Comparison of “Inside-Channel” and “On-Dielectric” Source Contact Modifications on the Performance of the Vertical Organic Field Effect Transistors

Simulation Study on Comparison of “Inside-Channel” and “On-Dielectric” Source Contact Modifications on the Performance of the Vertical Organic Field Effect Transistors

Achieving Ambipolar Transport Characteristics in the n-WS2 Channel via Remote p-Doping and its Enhancement-Mode Ambipolar Field-Effect Transistor Operation

Achieving Ambipolar Transport Characteristics in the n-WS₂ Channel via Remote p-Doping and its Enhancement-Mode Ambipolar Field-Effect Transistor Operation

Thieno[3,2-b]thiophene flanked para-azaquinodimethane π-extended aromatic-quinoidal polymers

A series of thieno[3,2-b]thiophene (TT) flanked para-azaquinodimethane (p-AQM) based quinoidal conjugated polymers PAQM2TT-T, PAQM2TT-BT and PAQM3TT were designed in a strategy to extend the aromatic-quinoidal π-system. The three polymers were synthesized by Stille polycondensation, and their opto-electronic properties and device performance in field-effect transistors have been explored. From absorption spectroscopy, the polymers show low bandgaps (1.54–1.57 eV) and high HOMO energy levels. They exhibit typical p-type behavior according to the results of the characterization of the field-effect transistors with average charge carrier mobilities of 0.08 cm2 V−1 s−1 for PAQM2TT-T, 0.12 cm2 V−1 s−1 for PAQM2TT-BT and 0.05 cm2 V−1 s−1 for PAM3TT. This report presents an alternative π-extended quinoidal-donor strategy to control the molecular design and properties of new p-AQM-based conjugated polymers.

Contact Resistance Engineering in WS2-Based FET with MoS2 Under-Contact Interlayer: A Statistical Approach.

One of the primary factors hindering the development of 2D material-based devices is the difficulty of overcoming fabrication processes, which pose a challenge in achieving low-resistance contacts. Widely used metal deposition methods lead to unfavorable Fermi level pinning effect (FLP), which prevents control over the Schottky barrier height at the metal/2D material junction. We propose to harness the FLP effect to lower contact resistance in field-effect transistors (FETs) by using an additional 2D interlayer at the conducting channel and metallic contact interface (under-contact interlayer). To do so, we developed a new approach using the gold-assisted transfer method, which enables the fabrication of heterostructures consisting of TMDs monolayers with complex shapes, prepatterned using e-beam lithography, with lateral dimensions even down to 100 nm. We designed and demonstrated tungsten disulfide (WS2) monolayer-based devices in which the molybdenum disulfide (MoS2) monolayer is placed only in the contact area of the FET, creating an Au/MoS2/WS2 junction, which effectively reduces contact resistance by over 60% and improves the Ion/Ioff ratio 10 times in comparison to WS2-based devices without MoS2 under-contact interlayer. The enhancement in the device operation arises from the FLP effect occurring only at the interface between the metal and the first layer of the MoS2/WS2 heterostructure. This results in favorable band alignment, which enhances the current flow through the junction. To ensure the reproducibility of our devices, we systematically analyzed 160 FET devices fabricated with under-contact interlayer and without it. Statistical analysis shows a consistent improvement in the operation of the device and reveals the impact of contact resistance on key FET performance indicators.

Enhancing the Performance of MoS2 Field-Effect Transistors Using Self-Assembled Monolayers: A Promising Strategy to Alleviate Dielectric Layer Scattering and Improve Device Performance.

Field-effect transistors (FETs) based on two-dimensional molybdenum disulfide (2D-MoS2) have great potential in electronic and optoelectronic applications, but the performances of these devices still face challenges such as scattering at the contact interface, which results in reduced mobility. In this work, we fabricated high-performance MoS2-FETs by inserting self-assembling monolayers (SAMs) between MoS2 and a SiO2 dielectric layer. The interface properties of MoS2/SiO2 were studied after the inductions of three different SAM structures including (perfluorophenyl)methyl phosphonic acid (PFPA), (4-aminobutyl) phosphonic acid (ABPA), and octadecylphosphonic acid (ODPA). The SiO2/ABPA/MoS2-FET exhibited significantly improved performances with the highest mobility of 528.7 cm2 V-1 s-1, which is 7.5 times that of SiO2/MoS2-FET, and an on/off ratio of ~106. Additionally, we investigated the effects of SAM molecular dipole vectors on device performances using density functional theory (DFT). Moreover, the first-principle calculations showed that ABPA SAMs reduced the frequencies of acoustic and optical phonons in the SiO2 dielectric layer, thereby suppressing the phonon scattering to the MoS2 channel and further improving the device's performance. This work provided a strategy for high-performance MoS2-FET fabrication by improving interface properties.

Achieving High-Performance Polymer-Wrapper-Free Aligned Carbon Nanotube Field-Effect Transistors Through Degradable Polymer Wrapping and Efficient Removal Techniques.

Semiconducting carbon nanotubes (s-CNTs) have emerged as a promising alternative to traditional silicon for ultrascaled field-effect transistors (FETs), owing to their exceptional properties. Aligned s-CNTs (A-CNTs) are particularly favored for practical applications due to their ability to provide higher driving current and lower contact resistance compared with individual s-CNTs or random networks. Achieving high-semiconducting-purity A-CNTs typically involves conjugated polymer wrapping for selective separation of s-CNTs, followed by self-assembly techniques. However, the presence of the polymer wrapper on A-CNTs can adversely impact electrical contact, gating efficiency, carrier transport, and device-to-device variations, necessitating its complete removal. While various methods have been explored for polymer removal, accurately characterizing the extent of removal remains a challenge. Traditional techniques such as absorption spectroscopy and X-ray photoelectron spectroscopy (XPS) may not accurately depict the remaining polymer content on A-CNTs due to their inherent detection limits. Consequently, the performance of FETs based on pure polymer-wrapper-free A-CNTs is unclear. In this study, we present an approach for preparing high-semiconducting-purity and polymer-wrapper-free A-CNTs using poly[(9,9-dioctylfluorenyl-2,7-dinitrilomethine)-(9,9-dioctylfluorenyl-2,7-dimethine)] (PFO-N-PFO), a degradable polymer, in conjunction with a modified dimension-limited self-alignment process (m-DLSA). Comprehensive transmission electron microscopy (TEM) characterizations, complemented by absorption and XPS characterizations, provide robust evidence of the successful near-complete removal of the polymer wrapper via a cleaning procedure involving acidic degradation, hot solvent rinsing, and vacuum annealing. Furthermore, top-gated FETs based on these high-semiconducting-purity and polymer-wrapper-free A-CNTs exhibit good performance metrics, including an on-current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω·μm, and negligible hysteresis, representing a significant advancement in the CNT-based FET technology.

Harnessing Compositional Gradients to Elucidate Phase Behaviors toward High Performance Polymer Semiconductor Blends.

Polymer semiconductor/insulator blends offer a promising avenue to achieve desired mechanical properties, environmental stability, and high device performance in organic field-effect transistors. A comprehensive understanding of process-structure-property relationships necessitates a thorough exploration of the composition space to identify transitions in performance, morphology, and phase behavior. Hence, this study employs a high-throughput gradient thin film library, enabling rapid and continuous screening of composition-morphology-device performance relationships in conjugated polymer blends. Applied to a donor-acceptor copolymer blend, this technique efficiently surveys a broad composition range, capturing trends in device performance across the gradient. Furthermore, characterizing the gradient library using microscopy and depth profiling techniques pinpointed composition-dependent transitions in morphology. To validate the results and gain deeper insights, uniform-composition experiments were conducted on select compositions within and outside the gradient range. Depth profiling experiments on the constant composition films unveil the presence of the semiconducting polymer at the air interface, with apparent enrichment of the semiconductor at the substrate interface at low ratios of the semiconducting component, transitioning to a more even distribution within the bulk of the film at higher ratios. The generalizability of the gradient approach was further confirmed by its application to a homopolymer under different solution processing conditions.

Influence of High-κ Dielectrics Integration on ALD-Based MoS2 Field-Effect Transistor Performance.

The integration of high-κ dielectrics on MoS2 field-effect transistors (FETs) is essential for the realization of MoS2 in ultrascaled nanoelectronic devices and circuits. Most studies covering this topic are based on exfoliated MoS2 flakes or chemical vapor deposition (CVD) grown MoS2 films, whereas other techniques, such as atomic layer deposition (ALD), are also gaining attention for the growth of MoS2 in recent years. In this work, we grow large-area MoS2 by means of plasma-enhanced (PE-)ALD and evaluate the influence of high-κ dielectrics on the properties of ALD-based MoS2 FETs through electrical characterization combined with surface-chemical and high-resolution scanning transmission electron microscopy (HR-STEM) analyses. We grow HfO x , AlO x , or both by means of PE-ALD or thermal ALD on our fabricated devices and show that, in addition to the dielectric constant, three other major parameters related to the processing of the dielectrics can simultaneously affect the MoS2 FET electrical characteristics and govern its doping. These parameters are the stoichiometry of the dielectric, its carbon impurity content, and the degree to which the MoS2 surface oxidizes upon the dielectric growth. When grown at 100 °C, our HfO x films are oxygen-vacant whereas our AlO x films are oxygen-rich. In addition, carbon impurities are incorporated into the dielectrics at low deposition temperatures, being one of the likely causes of the MoS2 FET overall n-type performance in all of the studied cases. Our investigations also reveal that PE-ALD of HfO x or AlO x oxidizes the MoS2 surface, whereas thermal ALD AlO x leaves MoS2 almost intact. In this respect, if thermal ALD AlO x of proper thickness is grown between MoS2 and HfO x , it can reduce the degree to which the MoS2 surface oxidizes by HfO x and meanwhile improve the total dielectric constant, altogether leading to the most optimal electrical performance in ALD-based MoS2 FETs.

Low Contact Resistance on Monolayer MoS2 Field-Effect Transistors Achieved by CMOS-Compatible Metal Contacts.

Contact engineering on monolayer layer (ML) semiconducting transition metal dichalcogenides (TMDs) is considered the most challenging problem toward using these materials as a transistor channel in future advanced technology nodes. The typically observed strong Fermi-level pinning induced in part by the reaction of the source/drain contact metal and the ML TMD frequently results in a large Schottky barrier height, which limits the electrical performance of ML TMD field-effect transistors (FETs). However, at a microscopic level, little is known about how interface defects or reaction sites impact the electrical performance of ML TMD FETs. In this work, we have performed statistically meaningful electrical measurements on at least 120 FETs combined with careful surface analysis to unveil contact resistance dependence on interface chemistry. In particular, we achieved a low contact resistance for ML MoS2 FETs with ultrahigh-vacuum (UHV, 3 × 10-11 mbar) deposited Ni contacts, ∼500 Ω·μm, which is 5 times lower than the contact resistance achieved when deposited under high-vacuum (HV, 3 × 10-6 mbar) conditions. These electrical results strongly correlate with our surface analysis observations. X-ray photoelectron spectroscopy (XPS) revealed significant bonding species between Ni and MoS2 under UHV conditions compared to that under HV. We also studied the Bi/MoS2 interface under UHV and HV deposition conditions. Different from the case of Ni, we do not observe a difference in contact resistance or interface chemistry between contacts deposited under UHV and HV. Finally, this article also explores the thermal stability and reliability of the two contact metals employed here.

Nonideality in Arrayed Carbon Nanotube Field Effect Transistors Revealed by High-Resolution Transmission Electron Microscopy.

High density and high semiconducting-purity single-walled carbon nanotube array (A-CNT) have recently been demonstrated as promising candidates for high-performance nanoelectronics. Knowledge of the structures and arrangement of CNTs within the arrays and their interfaces to neighboring CNTs, metal contacts, and dielectrics, as the key components of an A-CNT field effect transistor (FET), is essential for device mechanistic understanding and further optimization, particularly considering that the current technologies for the fabrication of A-CNT wafers are mainly laboratory-level solution-based processes. Here, we conduct a systematic investigation into the microstructures of A-CNT FETs mainly via cross-sectional high-resolution transmission electron microscopy and tentatively establish a framework consisting of up to 11 parameters which can be used for structure-side quality evaluation of the A-CNT FETs. The parameter ensemble includes the diameter, length (or terminal), and density distribution of CNTs, radial deformation of CNTs, array alignment defects, surface crystallography facets of contact metal, thickness distribution of high-k dielectrics (HfO2), and the contact ratios for the CNT-CNT, CNT-metal, CNT-dielectric, and CNT-substrate interfaces. Enriched array alignment defects, i.e., bundle, stacking, misorientation, and voids, are observed with a total ratio sometimes up to ∼90% in pristine A-CNTs and even up to ∼95% after the device fabrication process. Thus, they are suggested as the prevalent performance-limiting factors for A-CNT FETs. Complex interfacial structures are observed at the CNT-CNT, CNT-metal contact, and CNT-high-k dielectric interfaces, making the local environment and the property of each component CNT involved in an A-CNT FET distinct from others in terms of the diameters, radial deformation, and interactions with the local surroundings (mainly through van der Waals interactions). The present study suggests further improvements on the fabrication technology of A-CNT wafers and devices and mechanistic investigations into the impacts of complex array alignment defects and interface structures on the electrical performance of A-CNT FETs as well.

Enhanced electrical performance in graphene field-effect transistors through post-annealing of high-k HfLaO gate dielectrics

High-k gate dielectrics have attracted a great deal of attention in the investigation of transistors due to their unique properties such as superior gate controllability. However, their integration into graphene field-effect transistors (GFETs) remains problematic and the physical mechanisms governing the performance of these devices are still not fully understood. In this study, the effects of post-annealing on GFETs utilizing the high-k HfLaO ternary oxide as the gate dielectric were comprehensively investigated. The HfLaO film was deposited on top of graphene by magnetron sputtering, and the device performance with various post-annealing temperatures was conducted. It was found that post-annealing temperature can effectively increase the dielectric constant through balancing the oxygen-vacancy defects and moisture absorption. Both the surface morphology of HfLaO and performance of GFETs were investigated, and the fabricated GFETs exhibit notable electrical performance enhancements. Specifically, GFETs with a 200 °C post-annealed HfLaO gate dielectric demonstrate the optimal device performance, featuring a minimal Dirac point voltage (VDirac) of 1.1 V and a minimal hysteresis (ΔVDirac) of 0.5 V. The extracted hole and electron mobilities are 4012 and 1366 cm2/V · s, respectively, nearly one order of magnitude higher than that of GFETs with as-deposited HfLaO. This work outperforms other existing GFETs utilizing high-k gate dielectric and chemical vapor deposition grown graphene in terms of both carrier mobility and on–off ratio. It is also noted that the excessive post-annealing temperature can negatively impact the GFET performance through introducing oxygen vacancies, increasing the surface roughness, lowering the breakdown voltage, and inducing recrystallization.

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

Simulations of Anisotropic Monolayer GaSCl for p-Type Sub-10 nm High-Performance and Low-Power FETs.

Two-dimensional materials have been extensively studied in field-effect transistors (FETs). However, the performance of p-type FETs has lagged behind that of n-type, which limits the development of complementary logical circuits. Here, we investigate the electronic properties and transport performance of anisotropic monolayer GaSCl for p-type FETs through first-principles calculations. The anisotropic electronic properties of monolayer GaSCl result in excellent device performance. The p-type GaSCl FETs with 10 nm channel length have an on-state current of 2351 μA/μm for high-performance (HP) devices along the y direction and an on-state current of 992 μA/μm with an on/off ratio exceeding 107 for low-power (LP) applications along the x direction. In addition, the delay-time (τ) and power dissipation product of GaSCl FETs can fully meet the International Technology Roadmap for Semiconductors standards for HP and LP applications. Our work illustrates that monolayer GaSCl is a competitive p-type channel for next-generation devices.

Photo-switching operation of MoS2 field effect transistor by photoisomerization of azobenzene in solution delivered on a microfluidic platform

Combining the photoisomerization of molecules with an electrical device is important for developing optoelectronic devices. Field effect transistors (FETs) with atomically thin channels are suitable for this purpose because the FET properties respond to chemical changes in molecules. Since the photoisomerization wavelength of the switching molecules can be tuned, complex logic operations can be realized if a specific molecule is delivered to the target FET of an integrated circuit. However, conventional techniques for transferring molecules, such as drop casting and sublimation, cannot efficiently realize this goal. In this study, we fabricated a MoS2 FET device combined with a microfluidic platform, wherein the MoS2 channel was in contact with the flow of an azobenzene solution in isopropyl alcohol as the solvent. UV radiation (365 nm) and thermal relaxation realize the cycle of trans- and cis-azobenzene states and the switching of the substantial FET properties. This study demonstrated the feasibility of using the solution for optical switching of the MoS2-FET, which can realize quick phase changes in the molecule and the delivery of the molecule to the target FET by a microfluidic platform.

Correction: Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Correction: Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Enhance Carrier Diffusion of Monolayer MoSe2 by Interface Engineering.

Two-dimensional materials hold great potentials for beyond-CMOS (complementary metal-oxide-semiconductor) electronical and optoelectrical applications, and the development of field effect transistors (FET) with excellent performance using such materials is of particular interest. How to improve the performance of devices thus becomes an urgent issue. The performance of FETs depends greatly on the intrinsic electrical properties of the channel materials, meanwhile the device interface quality, such as extrinsic scattering of charged impurities, charge traps, and substrate surface roughness have a great influence on the performance. In this paper, the impact of the interface quality on the carrier diffusion behaviors of monolayer (ML) MoSe2 has been investigated by using an in situ ultrafast laser technique to avoid the surface contamination during device fabrication process. Two types of self-assembled monolayers (SAMs) are introduced to modify the gate dielectric surface through an interface engineering approach to obtain chemical-stable interfaces. The results showed that the transport properties of ML MoSe2 were enhanced after interface engineering, for example, the carrier mobility of ML MoSe2 was improved from ∼59.4 to ∼166.5 cm2 V-1 s-1 after the SAM modification. Meanwhile, the photocarrier dynamics of ML MoSe2 before and after interfacial engineering were also carefully studied. Our studies provide a feasible method for improving the carrier diffusion behaviors of such materials, and making them suited for application in future integrated circuit.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.