DRAM Performance Research Articles

INNOVATION IN 1T1C FRAM TECHNOLOGIES FOR ULTRA HIGH RELIABLE MEGA DENSITY FRAM AND FUTURE HIGH DENSITY FRAM

ABSTRACT FRAM whose cell structure and operation is almost identical to DRAM, can ideally realize cell size and performance of DRAM. However, the density and performance of current FRAM still fall far behind those of DRAM. In this paper, innovative 1T1C FRAM technologies for ultra high reliable mega density FRAMs and future high density FRAMs are discussed. A novel electrode technology has been proved to guarantee 175°C, 10 years retention lifetime and more than 1E13 endurance lifetime of mega density 1T1C, COB FRAM with the cell size of 15F2 at 250 nm technology node. Furthermore, a cell size of 12F2 at 150 nm technology node has successfully been realized by developing innovative 200 nm thick capacitor stack technologies and novel capacitor etching technologies. Finally, critical issues of 3-D capacitor arising from 3-dimensional deposition, such as step coverage and film uniformity have been greatly improved by the modification of the MOCVD PZT feeding source and a newly introduced noble metal atomic layer deposition technology.

Efficient address remapping in distributed shared-memory systems

As processor performance continues to improve at a rate much higher than DRAM and network performance, we are approaching a time when large-scale distributed shared memory systems will have remote memory latencies measured in tens of thousands of processor cycles. The Impulse memory system architecture adds an optional level of address indirection at the memory controller. Applications can use this level of indirection to control how data is accessed and cached and thereby improve cache and bus utilization and reduce the number of memory accesses required. Previous Impulse work focuses on uniprocessor systems and relies on software to flush processor caches when necessary to ensure data coherence. In this paper, we investigate an extension of Impulse to multiprocessor systems that extends the coherence protocol to maintain data coherence without requiring software-directed cache flushing. Specifically, the multiprocessor Impulse controller can gather/scatter data across the network while its coherence protocol guarantees that each gather request gets coherent data and each scatter request updates every coherent replica in the system. Our simulation results demonstrate that the proposed system can significantly outperform conventional systems, achieving an average speedup of 9X on four memory-bound benchmarks on a 32-processor system.

DRAM performance as a function of its structure and memory stream locality

This paper studies the performance of a DRAM component as a function of its structure and the locality of the memory stream. We present a method and a tool for retrieving scalar values for temporal and spatial locality and discuss caches as locality filters. Combinations of cache systems and DRAM configurations having varying number of banks are simulated, and the locality of the DRAM input memory stream is analyzed. The results show that there is a usable amount of locality in the post-cache memory stream, but it is poorly utilized by the current DRAM structures. The developed scalar metrics are found to be suitable for outlining and understanding the DRAM performance. Analyzing locality and considering possibilities to utilize it by DRAMs will become essential in the future, as the DRAM row access time becomes increasingly dominant.

Data prefetch mechanisms

The expanding gap between microprocessor and DRAM performance has necessitated the use of increasingly aggressive techniques designed to reduce or hide the latency of main memory access. Although large cache hierarchies have proven to be effective in reducing this latency for the most frequently used data, it is still not uncommon for many programs to spend more than half their run times stalled on memory requests. Data prefetching has been proposed as a technique for hiding the access latency of data referencing patterns that defeat caching strategies. Rather than waiting for a cache miss to initiate a memory fetch, data prefetching anticipates such misses and issues a fetch to the memory system in advance of the actual memory reference. To be effective, prefetching must be implemented in such a way that prefetches are timely, useful, and introduce little overhead. Secondary effects such as cache pollution and increased memory bandwidth requirements must also be taken into consideration. Despite these obstacles, prefetching has the potential to significantly improve overall program execution time by overlapping computation with memory accesses. Prefetching strategies are diverse, and no single strategy has yet been proposed that provides optimal performance. The following survey examines several alternative approaches, and discusses the design tradeoffs involved when implementing a data prefetch strategy.

Effects of A.C. Stress on Charge and Voltage Decay Rates of PZT Thin Film Capacitors for DRAM Applications

ABSTRACTA PZT thin film capacitor displays a reduction in the charge storage density (Qc') after the device has undergone pulsed electrical stress. This changes the charge-voltage relationship for the devices. The effect of this change in the Q-V relationship on the DRAM READ time is described. Measurements of the charge and voltage decay rates have been previously identified as ideal techniques for characterizing signal loss. For the first time the effects of electrical stress on these rates have been studied. While the charge decay rate decreases with an increase in the number of stress cycles for both the bipolar and unipolar stress, the voltage decay rate decreases after unipolar stress but it increases for bipolar stress at lower stress voltages. The implications of these results on the DRAM performance shall be discussed.

Variable V/sub CC/ design techniques for battery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V/sub CC/ level; (2) compensation of DC generators, V/sub BB/ and V/sub PP/, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V/sub CC/ variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M*8) by simulation. >

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance

The advantage of BiCMOS technology over CMOS technology in terms of the access time and the power dissipation is demonstrated for a 1.3- mu m 1-Mb DRAM with a TTL (transistor-transistor logic) interface. Two key results are obtained. One is that a BiCMOS driver achieves a 23% lower delay time and 28% lower power dissipation compared with a CMOS driver. This is due to the inherently small input gate capacitance of the BiCMOS inverter and the small number of inverter stages required to make the BiCMOS driver. The other result is that a 1-Mb BiCMOS DRAM incorporating the BiCMOS driver provides higher performance in terms of a 36% faster access time and 24% lower power dissipation after fabrication process deviations and temperature changes. The resistance to the process deviations and temperature changes of the BiCMOS is responsible for such excellent performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V/sub DD/ bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V/sub DD/. The 2/3-V/sub DD/ sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V/sub DD/ sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V/sub DD/ sensing with a limited bit-line swing has several distinct advantages over the half-V/sub DD/ sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>