Performance Of Double Gate MOSFET Research Articles

Investigating the Effects of Channel Length and High-K Dielectric Materials on the Performance of Double-Gate MOSFETs

Investigating the Effects of Channel Length and High-K Dielectric Materials on the Performance of Double-Gate MOSFETs

Effects of Non-Uniform Channel Geometry on Double-Gate MOSFET Performance

A Double-gate (DG) MOSFET with non-uniform channel (NUC) geometry, that is, the silicon thickness of embedded in double-gate is varied linearly from drain to source, is proposed. To quantitatively assess the effects of the NUC geometry on electrical characteristics of DG MOSFETs, the short-channel effects (SCEs) and the on-state current are numerically calculated for the device with different non-uniform channel thickness, channel length and gate oxide thickness respectively. To the proposed structure, the SCEs are suppressed, the subthreshold swing becomes smaller and the on-state current is significantly improved when the thickness of silicon lied at source becomes thinner, showing better performances than the conventional DG MOSFETs.

Effects of Non-Uniform Channel Geometry on Double-Gate MOSFET Performance

Effects of Non-Uniform Channel Geometry on Double-Gate MOSFET Performance

ANALYTICAL MODELING OF DRAIN CURRENT, CAPACITANCE AND TRANSCONDUCTANCE IN SYMMETRIC DOUBLE-GATE MOSFETs CONSIDERING QUANTUM EFFECTS

An analytical model for double-gate (DG) MOSFETs considering quantum mechanical effects is proposed in this paper. Schrödinger and Poisson's equations are solved simultaneously using a variational approach. Solving the Poisson and Schrödinger equations simultaneously reveals quantum effects (QME) that influence the performance of DG MOSFETs. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion layer centroid, inversion charge, gate capacitance, drain current and transconductance. We systematically evaluate and analyze the parameters of DG MOSFETs considering QME. The analytical solutions are simple, accurate and provide good physical insight into the quantization caused by quantum confinement under various gate biases. The analytical results of this model are verified by comparing the data obtained with one-dimensional self-consistent numerical solutions of Poisson and Schrödinger equations known as SCHRED.

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Analog/RF performance of double-gate MOSFETs in the sub-20-nm regime is investigated using ATLAS device simulator. It is shown that graded channel dual material double gate (GCDMDG) achieves higher drain current, peak transconductance, and higher values of cutoff frequency at lower drain currents. This novel architecture also provides better intrinsic gain for an amplifier. A new analog/RF figure of merit, gain transconductance frequency product (GTFP) is proposed that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The peak GTFP is observed at the higher end of moderate inversion, slightly above threshold. The GCDMDG device outperforms in terms of GTFP and is more favorable for shorter channel length devices.

Device performance and optimization of decananometer long double gate MOSFET by Monte Carlo simulation

Using Monte Carlo simulation, device performance of double gate MOSFET with 25 nm-gate length is evaluated. The influences of the body thickness, of the gate overlap or underlap, of the oxide thickness, of the back gate length, and of the RC parasitic effects have been investigated. We show that well-tempered devices with excellent subthreshold behaviour and good dynamic operation may be achieved with 10 nm-thick body if the gate-source/drain overlap is reduced to 0 and parasitic RC effects are controlled. To boost performance and to obtain greater allowance to parasitic RC effects, strained body may be used. Finally, the scaling strategy resulting from the study of 25 nm-long devices is successfully applied to design double gate MOSFET with shorter gate lengths.

Effects of the inversion-layer centroid on the performance of double-gate MOSFETs

The role of the inversion-layer centroid in a double-gate metal-oxide-semiconductor field-effect-transistor (DGMOSFET) has been investigated. The expression obtained for the inversion charge is similar to that found in conventional MOSFETs, with the inversion-charge centroid playing an identical role. The quantitative value of this magnitude has been analyzed in volume-inversion transistors and compared with the value obtained in conventional MOSFETs. The minority-carrier distribution has been found to be even closer to the interfaces in volume-inversion transistors with very thin films, and therefore, some of the advantages assumed for these devices are ungrounded. Finally, the overall advantages and disadvantages of double-gate MOSFET's over their conventional counterparts are discussed.