Performance Computing Systems Research Articles

Optimal robust configuration in cloud environment based on heuristic optimization algorithm

To analyze performance in cloud computing, some unpredictable perturbations that may lead to performance degradation are essential factors that should not be neglected. To prevent performance degradation in cloud computing systems, it is reasonable to measure the impact of the perturbations and propose a robust configuration strategy to maintain the performance of the system at an acceptable level. In this article, unlike previous research focusing on profit maximization and waiting time minimization, our study starts with the bottom line of expected performance degradation due to perturbation. The bottom line is quantified as the minimum acceptable profit and the maximum acceptable waiting time, and then the corresponding feasible region is defined. By comparing between the system’s actual working performance and the bottom line, the concept of robustness is invoked as a guiding basis for configuring server size and speed in feasible regions, so that the performance of the cloud computing system can be maintained at an acceptable level when perturbed. Subsequently, to improve the robustness of the system as much as possible, discuss the robustness measurement method. A heuristic optimization algorithm is proposed and compared with other heuristic optimization algorithms to verify the performance of the algorithm. Experimental results show that the magnitude error of the solution of our algorithm compared with the most advanced benchmark scheme is on the order of 10−6, indicating the accuracy of our solution.

Navigation Based on Hybrid Decentralized and Centralized Training and Execution Strategy for Multiple Mobile Robots Reinforcement Learning

In addressing the complex challenges of path planning in multi-robot systems, this paper proposes a novel Hybrid Decentralized and Centralized Training and Execution (DCTE) Strategy, aimed at optimizing computational efficiency and system performance. The strategy solves the prevalent issues of collision and coordination through a tiered optimization process. The DCTE strategy commences with an initial decentralized path planning step based on Deep Q-Network (DQN), where each robot independently formulates its path. This is followed by a centralized collision detection the analysis of which serves to identify potential intersections or collision risks. Paths confirmed as non-intersecting are used for execution, while those in collision areas prompt a dynamic re-planning step using DQN. Robots treat each other as dynamic obstacles to circumnavigate, ensuring continuous operation without disruptions. The final step involves linking the newly optimized paths with the original safe paths to form a complete and secure execution route. This paper demonstrates how this structured strategy not only mitigates collision risks but also significantly improves the computational efficiency of multi-robot systems. The reinforcement learning time was significantly shorter, with the DCTE strategy requiring only 3 min and 36 s compared to 5 min and 33 s in the comparison results of the simulation section. The improvement underscores the advantages of the proposed method in enhancing the effectiveness and efficiency of multi-robot systems.

Analysis of the parasitic capacitance effects on the layout of latch-based sense amplifiers for improving SRAM performance

Static random-access memory (SRAM) technology is utilized in designing cache memory to enhance the processing performance of computer systems. The sense amplifier (SA) circuit, a crucial component of memory design, significantly impacts data access time and power consumption. In comparison to conventional differential sense amplifiers (DSA) designs, latch-based sense amplifiers (LSA) used in memory-based computing platforms have specific requirements, including robust noise resistance in harsh working environments and low power consumption, particularly for internet of thing (IoT) embedded computing applications. However, the performance can be degraded due to various factors that arise during the layout, such as conductor resistance or the development of parasitic capacitance. Therefore, this study employs low-voltage 22 nm UMC CMOS technology for LSA design layout and analyzes the factors influencing design performance post-layout process. Layout design optimization techniques are applied to mitigate the impact of parasitic capacitance on important signal lines such as data line/data line bar (DLL/DLLB). Based on the performance analysis results, it is possible to achieve a reduction in power consumption of up to 15% and a 5% decrease in read delay time by implementing circuit layout LSA design optimization techniques.

CyberProbe-A Framework for Assessing System Security

In an age dominated by digital connectivity, protecting computer systems from increasing cyber attacks has become an important issue. The research presented here introduces “CYBERPROBE,” a well-designed method for security assessment. CYBERPROBE evaluates the performance of computer systems in various areas by combining process and state processes. The framework uses a variety of approaches to security, both procedural and procedural. CYBERPROBE strives to give companies a complete view of their security using simple penetration testing, vulnerability assessment and threat intelligence. The framework is flexible enough to adapt to the changing needs of today's IT systems by supporting a variety of architectures and configurations. This research article describes the main features, tools, methods and application scenarios of CYBERPROBE. The basis of the CYBERPROBE design is a comprehensive evaluation of existing security measures, highlighting their unique features and different elements. Key Words: CyberProbe, Cybersecurity, SQL Map, Nmap, snipper.

Temperature effect on a weighted vortex spin-torque nano-oscillator for neuromorphic computing

In this work, we present fabricated magnetic tunnel junctions (MTJs) that can serve as magnetic memories (MMs) or vortex spin-torque nano-oscillators (STNOs) depending on the device geometry. We explore the heating effect on the devices to study how the performance of a neuromorphic computing system (NCS) consisting of MMs and STNOs can be enhanced by temperature. We further applied a neural network for waveform classification applications. The resistance of MMs represents the synaptic weights of the NCS, while temperature acts as an extra degree of freedom in changing the weights and TMR, as their anti-parallel resistance is temperature sensitive, and parallel resistance is temperature independent. Given the advantage of using heat for such a network, we envision using a vertical-cavity surface-emitting laser (VCSEL) to selectively heat MMs and/or STNO when needed. We found that when heating MMs only, STNO only, or both MMs and STNO, from 25 to 75 °C, the output power of the STNO increases by 24.7%, 72%, and 92.3%, respectively. Our study shows that temperature can be used to improve the output power of neural networks, and we intend to pave the way for future implementation of a low-area and high-speed VCSEL-assisted spintronic NCS.

Optimasi Kinerja Sistem Komputer: Pendekatan Ilmiah untuk Meningkatkan Produktivitas Teknologi

This research investigates the effectiveness of new methods in improving computer system performance through a rigorous scientific approach. The research method applied includes the steps of data collection, implementation of new methods, data analysis, and evaluation of results. The research results show that the proposed innovative approach successfully improves the performance of the computer system in various test scenarios. Key findings include significant improvements in data processing speed, with increased system responsiveness and more optimal resource use efficiency. Statistical analysis shows a 25% increase in data processing speed and up to 20% improved resource usage. These results provide a strong empirical basis for the recognition of a scientific approach in improving computer system performance, as well as demonstrating the potential for further application in the context of computer system performance optimization. Thus, this research provides a valuable contribution to the understanding and practice of computer system performance optimization.

Approximations to Study the Impact of the Service Discipline in Systems with Redundancy

As job redundancy has been recognized as an effective means to improve performance of large-scale computer systems, queueing systems with redundancy have been studied by various authors. Existing results include methods to compute the queue length distribution and response time but only when the service discipline is First-Come-First-Served (FCFS). For other service disciplines, such as Processor Sharing (PS), or Last-Come-First-Served (LCFS), only the stability conditions are known. In this paper we develop the first methods to approximate the queue length distribution in a queueing system with redundancy under various service disciplines. We focus on a system with exponential job sizes, i.i.d. copies, and a large number of servers. We first derive a mean field approximation that is independent of the scheduling policy. In order to study the impact of service discipline, we then derive refinements of this approximation to specific scheduling policies. In the case of Processor Sharing, we provide a pair and a triplet approximation. The pair approximation can be regarded as a refinement of the classic mean field approximation and takes the service discipline into account, while the triplet approximation further refines the pair approximation. We also develop a pair approximation for three other service disciplines: First-Come-First-Served, Limited Processor Sharing and Last-Come-First-Served. We present numerical evidence that shows that all the approximations presented in the paper are highly accurate, but that none of them are asymptotically exact (as the number of servers goes to infinity). This makes these approximations suitable to study the impact of the service discipline on the queue length distribution. Our results show that FCFS yields the shortest queue length, and that the differences are more substantial at higher loads.

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

With the expanding computer application scenarios and increasing computational demands, optimizing 16-bit multiplication is an important and meaningful research topic. In this paper, we take advantage of the parallel computing property of Wallace tree and the advantage of bit-level operation of Booth algorithm to perform certain optimization on 16-bit multiplier. In this paper, a series of basic modules are firstly constructed as the basic framework of the multiplier, and then the optimization module is designed by using Booth algorithm and Wallace tree, and they are combined to obtain a multiplier with improved computational accuracy, reduced computational complexity, reduced delay, and improved computational efficiency compared with the traditional multiplier. The significance of the optimized multiplier implementation is to increase the computational speed, improve the chip resource utilization, reduce the power consumption and energy consumption, and meet the demand of complex applications, which is of great significance to improve the performance and efficiency of computer systems.

Mengevaluasi Efisiensi Pengontrol Input-Output dalam Arsitektur Komputer Modern

Input and output devices are a system that exists on a computer. A computer is a system consisting of various specific components. These components will later be connected to each other and work together, to carry out processes so that they can produce information. In general, the function of a computer is to receive, process and produce data output, various forms of information in the form of text, audio, images or video. The method used in this research is an adapted literature study, and the research flow is described as follows. Figure 1 shows the data collection method used in this research. The purpose of this data collection is to obtain data that will be analyzed and processed so that any existing problems can be found and it is hoped that this research will find solutions to these problems. To collect data, study the literature. This research uses hardware and software to prove the input devices and output devices that are usually used in organizing computers. The characteristics of the I/O system are influenced by the technology of other components, for example the processor. The performance of the I/O system is more complex than the processor. Therefore, increasing CPU time without directly increasing I/O time does not necessarily improve system I/O performance. Computer system performance can be improved by improving hardware and software component technology. In this research, the focus is on I/O device performance, specifically I/O time. This research examines the relationship between CPU time, I/O time, and elapsed time. The results show that increasing CPU time results in increasing I/O time. I/O system performance is very important for computer users. Response time, also known as total elapsed time, is an important performance measure, especially for single-user and personal computers. In commercial computing, high throughput and short response times are required. Behavior, partners, and data rate are three characteristics used to evaluate I/O systems. The performance of a computer system is determined by various factors, including different users, performance measures, and aspects of the system. Performance improvements can be achieved by improving hardware factors that support overall system performance. Performance measurement can be done through response time (execution time) or throughput. Response time aims to minimize the time between starting and completing a task, while higher throughput can be achieved by serving multiple requests simultaneously. Based on research, it can be concluded that the quality of input, process and output in Islamic educational institutions is influenced by various factors. Student input is critical in determining the quality of education, and the institution has implemented a selective process to ensure the admission of motivated and dedicated students. The educational process is characterized by the application of discipline, adherence to schedules, and the instillation of religious values. The institution's output is reflected in the academic achievements of its students, as well as their motivation and participation in various competitions and activities. This research uses a qualitative approach with a case study method, collecting data through documentation and observation. Data analysis was carried out using triangulation and interpreted qualitatively. This study highlights the importance of a holistic approach to education, integrating religious values, community support, and parental involvement to improve the quality of education.

A Utilization Based Genetic Algorithm for virtual machine placement in cloud systems

Due to the increasing demand for cloud computing and related services, cloud providers need to come up with methods and mechanisms that increase the performance, availability and reliability of data centers and cloud systems. Server virtualization is a key component to achieve this, which enables sharing of resources of a single physical machine among multiple virtual machines in a totally isolated manner. Optimizing virtualization has a very significant effect on the overall performance of a cloud computing system. This requires efficient and effective placement of virtual machines into physical machines. Since this is an optimization problem that involves multiple constraints and objectives, we propose a method based on genetic algorithms to place virtual machines into physical servers of a data center. By considering the utilization of machines and node distances, our method, called Utilization Based Genetic Algorithm (UBGA), aims at reducing resource waste, network load, and energy consumption at the same time. We compared our method against several other placement methods in terms of utilization achieved, networking bandwidth consumed, and energy costs incurred, using an open-source, publicly available CloudSim simulator. The results show that our method provides better performance compared to other placement approaches.

Generalized aberration regularization in the single-lens computational imaging system design.

The restoration algorithm can reduce the aberration blur in the single-lens computational imaging system. The single lens and the restoration algorithm should be co-designed to improve the imaging performance of the whole computational imaging system. By investigating the influence of aberrations on computational imaging quality, we find there are aberrations that cannot be removed by restoration algorithm, which cause the loss of high-resolution information. However, such aberrations are not constrained in existing co-design methods. To solve this problem, we propose the generalized aberration regularization (GAR), which mainly constrains the aberrations that reduce the modulation transfer function (MTF) at the high frequency. Experimental results demonstrate that our approach can significantly improve the quality of high-resolution information in the recovery image compared with the existing co-design methods.

Optimization of system resilience in urban rail systems: Train rescheduling considering congestions of stations

In urban rail systems, unexpected events, due to equipment breakdown, extreme weather, etc., frequently cause the delay of trains and overcrowding of platforms, significantly affecting the service quality to passengers. Therefore, improving system resilience to recover to normal conditions more quickly has become a critical problem in the management of urban rail systems. In contrast to most previous studies that focused only on train rescheduling, our paper proposes optimizing the resilience of urban rail systems by considering the influence of delayed trains and overcrowded passenger flows. Specifically, we define a resilience-oriented quantitative evaluation index. Using the evaluation index as the objective function, we construct a mixed-integer nonlinear programming model. In our formulation, we consider a practical case in which the boarding and alighting of passengers at overcrowded stations may further delay trains. To solve the model, we develop a two-phase iterative optimization approach, in which phase 1 focuses on the adjustment of trains to enhance system resilience, and phase 2 evaluates the impact of passengers on the adjusted train schedule. Through the comparison of three different rescheduling methods, we prove the validity of the derived inequalities and our approach balances the computational time and system performance. Case studies are conducted on the Beijing Metro Line 1 to verify the effectiveness of the proposed approach. The results demonstrate that system resilience can be improved by as much as 39.7% using our optimization approach.

CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration

With the increasing of DRAM’s capacity, the refresh operation rapidly becomes a major concern to the performance of the current computational system. Moreover, conservative timing parameters adopted for access operations make an increasing amount of negative impact on system performance and energy efficiency. In this paper, we propose an in-situ charge detection and adaptive data restoration DRAM (CDAR-DRAM) architecture, which can dynamically adjust the refresh rate and relax the constraints on access timing by removing pessimistic timing margins for PVT variations. CDAR-DRAM employs a lowcost skewed-inverter-based detector to monitor the bitline voltage in runtime and estimate real-time timing parameters of cells. Based on the detector, an adaptive refresh and restore scheme (CDAR-ref) is presented, which progressively reduces the refresh rate and partially restores cells’ voltage just enough for cells with sufficient charge, thereby optimizing both refresh and restoration operations. Moreover, a supplementary adaptive access scheme (CDAR-acc) is presented, which detects the runtime charge level of recently-accessed rows and reduces access latency aggressively, benefitting workloads in a single-core system and memory nonintensive workloads in a multi-core system. CDAR’s flexibility allows the two schemes to be combined. The evaluation shows that in an 8-core system, the combined scheme improves performance and energy efficiency by 15.2% and 22.6%, respectively.

Review of Architecture and Model for Parallel Programming

Parallel programming has become a critical aspect of modern computer systems and applications. With the increasing demand for faster and more efficient computing, it is essential to have multiple parallel architectures and parallel models to choose from. Different parallel architectures, like SISD and MIMD, perform differently and offer different benefits. It is essential to have an understanding of these architectures to select the appropriate one for the specific application being developed. Similarly, different parallel models such as OpenMP allow developers to write parallel programs using high-level constructs. By leveraging these models, developers can focus on the algorithmic aspects of the program rather than giving attention to low-level details. In conclusion, understanding the different parallel architectures and parallel models available is necessary to develop efficient parallel programs and improve the performance of modern computer systems.

IUG‐based beam selection for wideband millimetre wave massive MIMO systems

AbstractBeam selection aims to select beams with large power and little inter‐user interference (IUI). In wireless communication scenarios, the levels of IUI are usually different, but, most existing beam selection methods apply the same beam selection criteria for all users, which is detrimental to maintain an attractive trade‐off between computational complexity and system performance. Considering the discrepancy of IUI comprehensively, this paper proposes a beam selection method based on interfering user grouping (IUG) for wideband millimetre‐wave massive multiple‐input multiple‐output (MIMO) systems. Firstly, a candidate beam set (CBS) is constructed in light of the sparsity and power distribution of the beamspace channel. Based on the CBS, all users are classified into non‐interfering users (NIUs), low‐interference users (LIUs) and high‐interference users (HIUs). For NIUs, the beams with large power are selected from CBS under the magnitude maximization (MM) criterion; for LIUs, a novel MM criterion with a tabu list is designed, which can effectively tackle the drawback of assigning shared beams in traditional MM; for HIUs, the incremental algorithm based on the sum‐rate maximization criterion is developed to find the optimal beams from CBS. Simulation results validate that the proposed IUG‐based method can obtain a good performance with lower computational complexity compared with the existing methods.

Task Computation Offloading for Multi-Access Edge Computing via Attention Communication Deep Reinforcement Learning

This paper investigates how to enhance the Multi-access Edge Computing (MEC) systems performance with the aid of device-to-device (D2D) communication computation offloading. By adequately exploiting a novel computation offloading mechanism based on D2D collaboration, users can efficiently share computational resources with each other. However, it is challenging to distinguish valuable information that truly promotes a collaborative decision, as worthless information can hinder collaboration among users. In addition, the transmission of large volumes of information requires high bandwidth and incurs significant latency and computational complexity, resulting in unacceptable costs. In this paper, we propose an efficient D2D-assisted MEC computation offloading framework based on Attention Communication Deep Reinforcement Learning (ACDRL), which simulates the interactions between related entities, including device-to-device collaboration in the horizontal and device-to-edge offloading in the vertical. Secondly, we developed a distributed cooperative reinforcement learning algorithm that includes an attention mechanism that skews computational resources towards active users to avoid unnecessary resource wastage in large-scale MEC systems. Finally, to improve the effectiveness and rationality of cooperation among users, we introduce a communication channel to integrate information from all users in a communication group, thus facilitating cooperative decision-making. The proposed framework is benchmarked, and the experimental results show that the proposed framework can effectively reduce latency and provide valuable insights for practical design compared to other baseline approaches.

Omega multistage interconnection network manages double-pattern traffic with a regulator and high-speed forwarding method

This study proposes a flexible and effective solution for developing high-performance multistage interconnection networks to maximize the performance of parallel computer systems, cloud computing infrastructure, grids, etc. An omega-type multistage interconnection network, consisting of regulated switchboxes, is used as a testbed to handle flexible two-class load patterns. The wormhole routing method and a special forwarding technique controlled by a global regulator are adopted to alleviate internal ‘tree saturation’ caused by periodic hotspot traffic combined with uniform traffic. Simulation experiments prove that this concept reduces packet latency, and an additional layer inserted in the final stage further improves the network’s architecture.

Design and Analysis of XNOR-SRAM for In-Memory Computing

Abstract: The use of in-memory computing is a promising strategy with the potential to circumvent the von Neumann bottleneck and improve the overall performance of contemporary computer systems. In this study, the design and analysis of an innovative XNOR-SRAM cell for use in in-memory computing applications is presented. The performance of the suggested cell is assessed using crucial parameters such as cell ratio (CR), pull-up ratio (PR), static noise margin (SNM), write margin (WM), and read margin(RM)MA. Simulation and optimization of the proposed cell are carried out with the assistance of LTSPICE and the HSPICE tool . According to the findings, the XNOR-SRAM cell has greater performance when compared to the traditional 6T SRAM cell. This paves the way for the XNOR-SRAM cell to become a viable choice for in-memory computing.

FragTracer: Real-Time Fragmentation Monitoring Tool for F2FS File System.

Emerging hardware devices (e.g., NVMe SSD, RISC-V, etc.) open new opportunities for improving the overall performance of computer systems. In addition, the applications try to fully utilize hardware resources to keep up with those improvements. However, these trends can cause significant file system overheads (i.e., fragmentation issues). In this paper, we first study the reason for the fragmentation issues on an F2FS file system and present a new tool, called FragTracer, which helps to analyze the ratio of fragmentation in real-time. For user-friendly usage, we designed FragTracer with three main modules, monitoring, pre-processing, and visualization, which automatically runs without any user intervention. We also optimized FragTracer in terms of performance to hide its overhead in tracking and analyzing fragmentation issues on-the-fly. We evaluated FragTracer with three real-world databases on the F2FS file system, so as to study the fragmentation characteristics caused by databases, and we compared the overhead of FragTracer. Our evaluation results clearly show that the overhead of FragTracer is negligible when running on commodity computing environments.

Enhancing the lifetime of STT-RAM using compression based wear leveling technique

Driven memory requirements have increased with the increase in processor core count and working sets. Conventional memory technology such as SRAM (static random access memory) is unable to fulfill these demands. Alternate memory technologies such as NVM (non-volatile memory) have been proposed to fulfill the demands of higher memory usage due to its huge storage capacity and less leakage power. Though NVM is having the above advantages, it is limited in performance due to write restrictions. The write restriction directly affects the cache lifetime, which is an important parameter for computer system performance. This paper explores a compression based wear leveling technique to overcome the limitations of write restriction and to improve the cache lifetime. The proposed method lessens the bit writes to be written and also distributes the write equally in the sets of the cache. The frequent pattern compression is used to reduce each word write based on defined pattern sets. The writes are spread within word to enable uniform distribution of writes. The bit transitions during the writes can be reduced further by identifying the existing cache line with minimum transitions to be placed. Wear leveling is implemented to enhance the cache endurance by equally distributing the incoming writes to all the cache blocks. The proposed method improves the lifespan by 42 %, 52 %, 75 % and 18 % with a 5 % area overhead compared to LER, TA_LRU, Equalwrites and Compression+EW techniques.