Performance Of Thin-film Transistors Research Articles

The Effect of Alkyl Chain Length in Organic Semiconductor and Surface Polarity of Polymer Dielectrics in Organic Thin-Film Transistors (OTFTs).

The interface between dielectric and organic semiconductor is critically important in determining organic thin-film transistor (OTFT) performance. Surface polarity of the dielectric layer can hinder charge transport characteristics, which has restricted utilization of polymeric dielectric materials containing polar functional groups. Herein, the electrical characteristics of OTFTs are analyzed depending on the alkyl chain length of organic semiconductors and surface polarity of polymer dielectrics. High-performance dibenzothiopheno[6,5-b:6',5'-f]thieno[3,2-b]thiophene (DBTTT) and newly synthesized its alkylated derivatives (C6-DBTTT and C10-DBTTT) are utilized as organic semiconductors. As dielectric layers, non-polar poly(1,3,5-trimethyl-1,3,5-trivinylcyclitrisiloxane) (pV3D3) and poly(2-cyanoethyl acrylate-co-diethylene glycol divinyl ether) [p(CEA-co-DEGDVE)] with polar cyanide functionality are utilized. The fabricated OTFTs with pV3D3 commonly exhibit the excellent charge transport characteristics. In addition, the OTFT performance is improved with lengthening the alkyl chain in organic semiconductors, which can be attributed to the molecular orientation of semiconductors. On the other hand, non-alkylated DBTTT OTFTs with polar p(CEA-co-DEGDVE) show relatively poor electrical characteristics, while their performance is drastically enhanced with the alkylated DBTTTs. The ultraviolet photoelectron spectroscopy (UPS) reveals that surface polarity of the dielectric layer can be abated with alkyl chain in organic semiconductors. It is believed that this study can provide a useful insight to optimize dielectric/semiconductor interface to achieve high-performance OTFTs.

Fabrication and investigation of the electrical performance of nitrogenated bilayer ZnO:N/ZnO thin-film transistors

In this study, a bilayer ZnO:N/ZnO thin-film transistors (TFTs) was designed to improve both the performance and stability of single-layer ZnO TFTs, using the effects of N-treatment on oxygen vacancy (VO) and the interface trap density. Bilayer ZnO:N/ZnO films and related TFTs were fabricated via radiofrequency magnetron sputtering in a mixture of Ar and N2 gas at 150 °C. The electrical performance and bias-stress stability were systematically investigated. The bilayer ZnO:N/ZnO TFT exhibited a linear field-effect mobility of 13.6 cm2/Vs, high current on-to-off ratio (Ion/Ioff) of 1 × 107, small threshold voltage (Vth) of 2.6 V, and low subthreshold swing of 0.32 V/decade compared with single-layer undoped ZnO and ZnO:N TFTs. Moreover, ZnO:N/ZnO TFT exhibited small threshold voltage shifts (∆Vth) of 0.8 and –0.9 V according to positive bias illumination stress and negative bias illumination stress measurements, respectively. X-ray photoelectron spectroscopy analysis showed that the N-treatment passivated the VO defects, reduced the density of interface traps, and controlled the carrier concentration. Thus, the performance and stability of the ZnO:N/ZnO TFTs were improved. Therefore, ZnO:N/ZnO TFTs have good application prospects in transparent thin-film electronics and flat-panel displays.

The influence of annealing atmosphere on sputtered indium oxide thin-film transistors

Indium oxide (In2O3) thin films sputtered at room temperature were annealed under different atmospheres and examined for thin-film transistor (TFT) active channel applications. The annealing process was performed in a rapid thermal annealing system at 350 °C under O2, Ar, forming gas (FG, 96% N2/4% H2), and N2. It was found that the annealed In2O3 TFTs exhibited high field-effect mobility (μ FE > 40 cm2 V−1s−1), high on/off current ratio (I on/off∼ 108), and controlled threshold voltage (V TH) for the enhancement- and depletion-mode operations. Note that the annealing atmosphere has a significant effect on the electrical performance of the In2O3 TFTs by inducing changes in oxygen-related species, particularly oxygen vacancies (VO) and hydroxyl/carbonate species (O–H/C–O). For the O2-, Ar-, FG-, and N2-annealed TFTs, μ FE was in increasing order accompanied by a negative shift in V TH, which is a result attributed to the larger VO in the In2O3 thin films. Furthermore, the ΔV TH of the FG-, and N2-annealed TFTs in a positive bias stress test was greater than that of the O2-, Ar-annealed devices, attributing to their lower density of O–H/C–O groups in the In2O3 thin films. Our results suggest that the annealing atmosphere contributes to the internal modifications of the In2O3 structure and in turn altered the electrical characteristics of TFTs. These annealed In2O3 TFTs with high performance are promising candidates for realizing large-area, transparent, and high-resolution displays.

Performance enhancement of solution-processed p-type CuI TFTs by self-assembled monolayer treatment

Self-assembled monolayer (SAM) treatment of gate dielectrics plays a key role in the improvement of the electrical performance of organic thin-film transistors (TFTs) by reducing the interface traps. However, it is rarely explored in inorganic TFTs owing to possible irreversible damage to very thin SAMs during the sputtering and high-temperature annealing processes that are often used to deposit inorganic materials. Here, the feasibility of performance enhancement of inorganic p-type Zn-doped CuI TFTs is explored by a SAM treatment using 3-aminopropyltriethoxysilane (APTES) on the gate dielectric. Our result shows that the TFT performance is significantly enhanced with a 50% reduction in the interface trap density, a 326% increase in the hole mobility from 0.38 to 1.24 cm2V-1s-1and a 5-fold increase in the current on/off ratio from 2.6 × 106 to 1.1 × 107. In addition, the bias stress stability of the TFTs after the treatment is dramatically enhanced by a factor of 10 due to the improved interface properties. The threshold voltage shift is reduced from +19.6 to +1.8 V after 3600 s positive bias stress. The simple yet effective interface treatment approach may have great potential in the fabrication of high-performance inorganic p-type electronic devices.

Performance and reliability improvement of all-solution processed indium zinc oxide thin-film transistor by UV irradiation treatment

Developing a low-temperature fabrication strategy for amorphous oxide semiconductors, such as amorphous indium zinc oxide (a-IZO) channel layers, for use in flexible oxide-based thin-film transistors (TFTs) is essential. In this work, high-performance and highly stable all-solution processed a-IZO TFTs were achieved by varying the duration of a photo-assisted combination treatment (UV combination treatment), which combines UV irradiation with a low heating temperature (115 °C) in an all-solution processed approach. From the experimental results, UV irradiation can activate the IZO source, drain, and gate electrodes which induces TFT switching. X-ray photoelectron spectroscopy analysis revealed oxygen vacancy (V o) generation after the UV combination treatment which increased the carrier concentration and improved the conductivity of IZO. All-solution processed a-IZO TFTs with high performance and stability, high mobility (µ) up to 17.45 cm2 V−1 s−1, threshold voltage (Vth) = −1.2 V, and subthreshold swing (SS) = 0.64 V dec−1, were obtained at a low temperature of 115 °C for 90 min treatment time. The stability behavior of self-aligned top-gate, top-contact a-IZO TFT fabricated by UV combination treatment was investigated under positive bias stress (PBS) and negative bias stress (NBS) with the smallest ΔV th of 2.4 V and 0.5 V for PBS and NBS, respectively. Our work shows that better stability indicated by the smaller ΔV th is achieved due to reduction of interface trap density and moisture-related impurities, in particular on the activated electrode area. As a result, it can be inferred that UV combination treatment is a simple and promising method to enhance the electrical and stability performance of a-IZO TFTs even with the low-temperature process, which is useful for flexible devices.

Performance and stability of Al-doped HfGaO thin-film transistors deposited by vapor cooling condensation system

In this work, to study the features of Al atomic ratio in Al2O3-doped HfGaO (referred as AlHfGaO) channel layers of thin-film transistors, the HfGaO and various AlHfGaO films were deposited at approximately 80 K using a vapor cooling condensation system. The oxygen vacancy defects resided in AlHfGaO films and the defect density in the resulting thin-film transistors decreased with an increase of the Al atomic ratio. As defects reduced, threshold voltage and on/off current ratio increased, while threshold voltage offset and subthreshold swing decreased. In terms of the threshold voltage offset, measured by positive gate bias stress and negative gate bias stress methods, as the stability parameter of thin-film transistors, the stability was improved by using a higher Al atomic ratio in the AlHfGaO channel layers due to the suppression of the charge trapping effect.

High Performance Amorphous In0.5Ga0.5O Thin‐Film Transistor Embedded with Nanocrystalline In2O3 Dots for Flexible Display Application

AbstractHigh‐performance, coplanar amorphous In0.5Ga0.5O (a‐IGO) thin film transistor (TFT) on a polyimide (PI) substrate deposited by spray pyrolysis (SP) is reported. The SP a‐IGO film deposited at 370 °C has less than 8% nanocrystalline‐In2O3 dots and a mass density of 6.6 g cm−3. The a‐IGO TFT on PI exhibits linear mobility over 30 cm2 V−1 s−1 and a negligible shift in threshold voltage (ΔVTH = <0.3 V) under positive bias (+20 V) at 60 °C for 1 h. The TFT performance is stable even when bent to a radius of ≈1 mm. The X‐ray photoelectron spectroscopy results of the SP a‐IGO deposited at 370 °C indicate the O‐vacancy (Vo) related defects of 25.79% and hydroxyl (OH) at less than 3%, indicating a good active/gate insulator interface. A seven‐stage ring oscillator made of SP a‐IGO TFTs exhibits a high oscillation frequency (>2.3 MHz) with a low propagation delay time of ≈30 ns per stage at a supply voltage (VDD) of 15 V. The fabricated gate shift register circuit works up to the last stage without any decrement of the input voltage (15 V) with rising and falling times less than 0.8 µs. Therefore, the coplanar a‐IGO TFT by SP deposited at 370 °C is a promising candidate for low‐cost, flexible TFT backplanes of foldable electronics.

Metal-induced lateral crystallization of germanium thin films

Recent advances in polycrystalline Ge layers formed through solid-phase crystallization have demonstrated carrier mobilities superior to those of single-crystal Si. In this study, we thoroughly examined the phenomenon of metal-induced lateral crystallization in Ge, a topic that had garnered significant attention in Si research and had shown promise in improving the performance of thin-film transistors. Of the 24 metals tested (Au, In, Bi, Pb, Ga, Ag, Al, Sn, Zn, Sb, Fe, Nb, Mg, Mn, Co, Cr, Mo, Zr, Cu, Ni, Pd, Ta, Ti, and W), 20 were found to promote the low-temperature (<400 °C) lateral growth of Ge layers on glass. Based on the reaction type (eutectic or compound), reaction temperatures, diffusion coefficients, and domain matching analyzed using a materials informatics method, the growth morphology was categorized into three types: alloy, dendrite, and uniform. The knowledge of metal-induced growth obtained in this study has broad implications for a variety of materials and holds potential for developing the next generation thin-film devices with common and inexpensive substrates.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

Effects of Ti Doping on the Electrical Properties and Gate-Bias Stability of Amorphous Zinc–Tin–Oxide Thin-Film Transistors

Multicationic oxide semiconductors are receiving considerable interest in electronic and optoelectronic devices owing to their tunability of physical properties by the cation compositions. Here, we investigated the effects of Ti doping on the electrical properties and gate-bias stability of amorphous zinc–tin–oxide (a-ZnSnO, Zn/Sn = 7:3) thin-film transistors (TFTs) using a cosputtering process. Particularly, by using cosputtering, controllable doping of Ti in a-ZnSnO films was possible in the range of 0.87–3.87 atom %. From various electrical analyses, it was found that the key metrics of Ti-doped ZnSnO (TiZnSnO) TFTs, such as field-effect mobility and gate-bias stability, were highly dependent on the Ti concentration, showing a mobility–stability tradeoff. Based on X-ray photoelectron spectroscopy analysis, the mobility–stability tradeoff is ascribed to the suppression of oxygen vacancy formation by Ti doping. Considering the overall electrical performance and stability of TiZnSnO TFTs, which were processed at 450 °C, the optimal Ti concentration was determined as ∼1.14 atom % with Zn, Sn, and O concentrations of 15.87, 22.92, and 60.07 atom %, respectively. The device exhibited a field-effect mobility of 8.2 cm2 V–1 s–1, a subthreshold slope of 0.208 V decade–1, an on/off ratio of 3.38 × 108, a hysteresis of 2.8 V, and a threshold voltage shift of +5.61 and −2.24 V under positive- and negative-bias stresses, respectively.

The improved properties of solution-based InGaSnO (IGTO) thin film transistor using the modification of InZnO (IZO) layer

For improving the properties of indium-gallium-tin oxide (IGTO) thin film transistors (TFTs) based on solution method, indium-zinc oxide (IZO) thin film was used as a modification layer. When IZO did not perform post-annealing, the performance improvement of bilayer TFTs was not significant. When IZO performed post-annealing, the performance improvement of the bilayer TFTs was obvious. We also compared the effects of annealing time on the performance of IGTO TFTs. The modifying effects of IZO and the suitable annealing time led to a great improvement in the performance of TFTs. The mobility was increased by about 10 times than monolayer IGTO (0.27 cm2V−1s−1→4.38 cm2V−1s−1), and the threshold voltage and subthreshold swing were also very small (0.60 V, 0.55). We attribute the performance improvement of dual active layer TFTs to two reasons. On the one hand, the modifying effects of IZO made the IGTO defect state less and the film denser. On the other hand, the bilayer TFTs form a heterojunction structure similar to 2-dimensional electron gas (2DEG), which enhanced the mobility of the TFTs. This paper provides a research basis for the process of preparing dual active layers by solution method, and provides a new idea for the performance improvement of IGTO.

Low-voltage solution-processed P-type Mg-doped CuI thin film transistors with NAND logic function

Low-voltage electric-double-layer (EDL) p-channel Mg-doped CuI thin-film-transistors (TFTs) have been fabricated on glass substrates at low temperatures. Electrical properties of the solution-processed CuI TFTs with different Mg doping concentrations were investigated. It is observed that compared to undoped CuI TFTs and Mg0.1Cu0.9Ix TFTs, Mg0.05Cu0.95Ix TFTs exhibit an excellent current on/off ratio of 1.1 × 105, a steep subthreshold swing of 21.78 mV/dec, a higher saturation field-effect mobility of 0.95 cm2 V−1 s−1, and the threshold voltage of 1.81 V. The high specific capacitance of 4.7 μF/cm2 is obtained in solution-processed chitosan dielectrics; when it was used as the gate dielectric instead of traditional SiO2, the operating voltage of TFTs can be reduced to 2.5 V. It is noteworthy that the NAND logic function has been realized on the dual in-plane-gate structure of such Mg0.05Cu0.95Ix-based TFTs. Finally, the effects of laser (λ = 638 nm) and negative bias stress (NBS) were observed on Mg0.05Cu0.95Ix TFTs. The transfer curves of the TFT drifted positively as the power of the laser progressively increased; the OFF-state current gradually increased as the NBS time became longer. This paper provides an effective way to improve the performance of p-channel CuI TFTs and indicates that Mg0.05Cu0.95Ix as a promising p-type material for next-generation high-performance low-power-consumption logic circuit applications.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

Here, we investigate the effect of increasing temperature on threshold voltage (VTH) stability in self-aligned coplanar amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs). An analytical model of the temperature dependency of VTH stability reveals the importance of device geometry and subgap density-of-state (DOS) reductions in highly stable a-IZTO TFTs. The validity of the analytical model is confirmed using experiments and technology computer-aided design simulations to predict quantitative relationships under various shifts in temperatures, subgap DOS, and VTH. The role of hydrogen impurity in performance and VTH stability is also examined. The incorporation of hydrogen in a-IZTO channels improves TFT performance and thermal stability (ΔVTH/ΔT = 3.18 mV/K) due to hydrogen’s role as a passivation center. However, excessive incorporation of hydrogen increases subgap DOS distribution, causing a slight deterioration in thermal stability (ΔVTH/ΔT = 3.31 mV/K). This suggests that hydrogen can be converted from a shallow donor to an acceptor-like deep trap state. Our findings inform future designs of stable oxide semiconductor TFTs in terms of thermal stability in emerging organic light-emitting diode, augmented and virtual reality, memory, logic, and monolithic three-dimensional applications.

Influence of indium doping on electrical performance of gallium oxide thin-film transistors

In the field of oxide semiconductor thin-film transistors (TFTs), the occurrence of charge trapping in the gate dielectric and interfaces presents significant challenges to their operational stability and reliability. In this study, we present high-performing amorphous Ga2O3 TFTs created using atomic layer deposition with varying indium doping concentrations. The channel length (Lch) and channel width (Wch) are 50 and 200 μm, respectively. As the Indium concentration increases from 0% to 60%, the charge trap density (Nit) decreases, resulting in a smaller hysteresis window. The TFTs with a doping concentration of 20% are particularly noteworthy, exhibiting high field-effect mobility (22.6 cm2 V−1 s−1), lower subthreshold swing (160 mV/dec) than amorphous Ga2O3 channel devices, a high on-off current ratio (109), an appropriate threshold voltage (−1 V), and a substantial output current (26 mA/mm at VGS = 16 V).

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

Low-voltage, solution-processed InZnO thin-film transistors with enhanced performance achieved by bilayer gate dielectrics

Fully solution-processed oxide thin-film transistors (TFTs) have shown a great potential in future printable electronics. However, high defect densities at the dielectric/channel interface have limited the simultaneous achievement of low operating voltage and high device performance. In this Letter, we study the effects of bilayer gate dielectrics in potential performance enhancement of solution-processed indium zinc oxide (IZO) TFTs. Several single and bilayer gate dielectrics are studied in terms of their physical and electrical properties. Compared with IZO TFTs using single-layer ZrOx gate dielectrics, optimized TFTs with ZrOx/AlOx gate dielectrics show an increase in carrier mobility and current on/off ratio by a factor of 3.5 and 27, respectively. The inner mechanisms of the performance enhancement are systematically studied, showing that the significantly improved TFT performance originates from the passivation effects of AlOx, which reduce the trap/defect states at the dielectric/channel interface by approximately an order of magnitude. With a low operating voltage of 2 V, a high mobility of over 10 cm2/V s, a subthreshold swing as low as 89 mV/dec, and a high current on/off ratio of &amp;gt;105, the reported devices might have a great potential in future low-cost, low-power printable electronics.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3 NL TFT showed remarkable electrical performance: μFE of 77.1 ± 0.67 cm2/(V s), VTH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and ION/OFF of 8.9 × 109 with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors

In recent years, high-k gate dielectrics have attracted increasing attention in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), due to the urge for stronger gate controllability in advanced applications of high integration density. In this work, the ultra-thin top-gate insulator of atomic-layer-deposited (ALD) HfOx was developed for the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs. Despite the good electrical characteristics of the 4-nm HfOx-gated a-IGZO transistor, its reliability is considerably poor and ascribed to the abundant interface defects, for example, oxygen vacancies. The interface reaction between HfOx and a-IGZO during the ALD process is clarified to be responsible for such defect generation. To prevent the oxygen-related reaction, the a-IGZO channel is pre-treated using the strong oxidizing plasma, contributing to significantly enhanced electrical stabilities. However, the further thinner HfOx would readily increase the gate leakage current, since the electron can easily tunnel through the ultra-thin HfOx due to the low conduction band offset between HfOx and AOS. The 4-nm ALD HfOx together with the pre-oxidization contributes to the optimal performance and stability of top-gate a-IGZO TFT.

Effects of Sn Doping on the Electrical Performance and Stability of Sub-V Operating Metal-Oxide Thin-Film Transistors Fabricated by Oxygen Annealing

The incorporation of Sn into a sol-gel-based indium-gallium-zinc oxide (IGZO) channel layer is investigated to improve the electrical characteristics and operational stability of amorphous metal-oxide thin-film transistors (oxide-TFTs). Sub-V operating Sn-doped IGZO-TFTs (IGZTO-TFTs) fabricated by solution-process under a high-pressure oxygen-enriched (O2) atmosphere exhibit significantly improved electrical properties such as a high linear field-effect mobility (11.5 cm2 V−1 s−1), high on/off ratio (up to 108), and low subthreshold swing (0.10 V/dec). The activation energy and density of states are determined to perform comparative analysis on the charge transport characteristics of the IGZTO-TFTs. Under both prolonged positive and negative bias illumination stresses, large shifts in threshold voltages of the IGZO-TFTs are reduced significantly after Sn doping. The suppressed formation of oxygen-related defect states affects the electrical characteristics and operational stability. This is verified by determining the proportional ratio of metal-oxygen bonding states in the O2-annealed IGZTO films.

43.2: Parasitic Capacitance Model for BGTC TFTs and Verification Using C‐V Measurements from Devices with Various Channel Dimensions

A model of the accumulation and depletion capacitance for a bottom gate top contact (BGTC) thin film transistors (TFT) with an etch stop layer (ESL) was presented. The model, which includes the parasitic capacitance due to device layout, was verified by comparison of measured data and modeled data for TFTs of various dimensions. Good agreement was seen between measured and modeled data, where the model underestimated the capacitance by 2% to 7%, depending on the device dimensions. The impact of the parasitic capacitance on estimates of the Debye length (λD ) are discussed and it is demonstrated that the relative error in the λD estimates is directly proportional to the ratio of the parasitic capacitance over the measured capacitance (CPAR/CM). The relative error was shown to increase as the ratio increases, leading to a larger underestimation of the λD. It was concluded that the parasitic capacitance to measured capacitance should be minimized for devices that are used for extraction of physical parameters from C‐V data. This is especially important in the case where the λD is a critical parameter in the optimization of TFT performance.