Performance Of Real-time Applications Research Articles

Coordinated Handover Initiation and Cross-Layer Adaptation for Mobile Multimedia Systems

A cross-layer mechanism to improve the performance of real-time applications over IEEE 802.16e metropolitan area networks is presented. The proposed mechanism uses channel quality and service quality information from the physical and medium access control layers, respectively, to determine the most suitable burst profile, transmission power level and media encoding rate for a connection, or even initialize a handover execution. The main contribution of this mechanism is the integration of the handover initiation into the cross layer logic, aiming to improve the overall system performance. Extensive simulation results show that the proposed mechanism offers significant performance improvement in terms of packet loss rate, power consumption, throughput, and system capacity.

Design of a real-time adaptive NURBS interpolator with axis acceleration limit

With recent advances in high-speed and high-accuracy machining, the NURBS interpolator has shown significant effect on dealing with the free-form curves and surfaces. The existing study aims at developing the adaptive interpolator which confines the chord error, the tangent acceleration, and jerk. However, the excessive axis acceleration is still unavoidable at the sharp corners and will deteriorate the contour accuracy. In this paper, a real-time adaptive NURBS interpolator considering the acc/dec capacity for each individual axis is developed to confine both the chord error and the axis acceleration. The maximum feasible feed and tangent acceleration range are deduced, respecting the given axis acc/dec limit. A two-stage feed determination scheme is applied to calculate the adaptive feed rate for each sampling period. A look-ahead window is utilized to improve the calculation performance for real-time application. Simulations and experiments are performed to verify the resulting feed rate, acc/dec profiles, and the real-time performance of the proposed interpolator.

Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications

While the average-case performance is important for general-purpose applications, worst-case performance is crucial for real-time systems to ensure schedulability and reliability. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can benefit both average-case and worst-case performance; however, the improvement on the worstcase execution time (WCET) is rather limited and inefficient. This paper presents two instruction prefetching approaches that are specially designed to enhance the worst-case performance, including the loop-based prefetching and WCET-oriented prefetching. Our experiments indicate that both instruction prefetching techniques can achieve better worst-case execution cycles than the Next-N-Line prefetching while having various impacts on the average-case performance.

Real‐time noise source identification using field programmable gate array technology.

Acoustic beamforming is usually used as an off-line analysis tool for noise source identification (NSI). The computational requirements of beamforming make real-time processing difficult to achieve in conventional NSI measurement systems. This limitation prevents conventional NSI measurement systems being used in applications like on-line monitoring. This paper presents the theory, design, and development of a real-time NSI measurement system based on reconfigurable I/O Field Programmable Gate Array (FPGA) technology. Some techniques used in applying beamforming analysis methods with an FPGA are outlined. Signal processing includes time filtering of input data and spatial beamforming with special treatment to obtain the best result. Pipelining methodology is used to make full use of the FPGA resources and reach high performance for real-time applications. Test examples are given to demonstrate the some applications for NSI.

Achieving Scalability in Real-Time Systems

Running real-time applications with a variable-speed processor can result in scheduling anomalies and permanent overloads. A proposed computational model varies task response times continuously with processor speed, enabling the system to predictably scale its performance during voltage changes. Mutually exclusive resources and nonpreemptive code can generate scheduling anomalies in a processor with dynamic voltage scaling, causing tasks to increase their response times when the processor runs at higher speeds. Even worse, decreasing the speed can cause a permanent overload that degrades system performance in an uncontrolled fashion. Such problems can be efficiently handled through a set of kernel mechanisms, including cyclic asynchronous buffers and elastic scheduling that let system designers scale the performance of real-time applications as a function of processor speed. As successfully done in the SHaRK kernel, both CABs and elastic scheduling can be easily implemented on top of any real-time operating system, as a middleware layer, and they should be included in current standards to develop embedded systems with real-time and energy requirements.

Joint end-to-end loss-delay hidden Markov model for periodic UDP traffic over the Internet

Performance of real-time applications on network communication channels is strongly related to losses and temporal delays. Several studies showed that these network features may be correlated and exhibit a certain degree of memory such as bursty losses and delays. The memory and the statistical dependence between losses and temporal delays suggest that the channel may be well modeled by a hidden Markov model (HMM) with appropriate hidden variables that capture the current state of the network. In this paper, an HMM is proposed that shows excellent performance in modeling typical channel behaviors in a set of real packet links. The system is trained with a modified version of the Expectation-Maximization (EM) algorithm. Hidden-state analysis shows how the state variables characterize channel dynamics. State-sequence estimation is obtained by the use of Viterbi algorithm. Real-time modeling of the channel is the first step to implement adaptive communication strategies.

QoS for high-performance SMT processors in embedded systems

Although simultaneous multithreading processors provide a good cost-performance tradeoff, they exhibit unpredictable performance in real-time applications. We present a resource management scheme that eliminates a major cause of performance unpredictability in SMTs, making them suitable for many types of embedded systems.

Homomorphic factorization of BRDF-based lighting computation

Several techniques have been developed to approximate Bidirectional Reflectance Distribution Functions (BRDF) with acceptable quality and performance for realtime applications. The recently published Homomorphic Factorization by McCool et al. is a general approximation approach that can be used with various setups and for different quality requirements.In this paper we propose a new technique based on the Homomorphic Factorization. Instead of approximating the BRDF, our technique factorizes the full lighting computation of an isotropic BRDF in a global illumination scenario. With this method materials in complex lighting situations can be simulated with only two textures by using commonly available computation capabilities of current graphics hardware.The new technique can also be considered as a generalized approach to several environment map prefiltering techniques. Existing prefiltering techniques are usually limited to specific BRDFs or require advanced hardware capabilities like 3D texturing. With the factorization only common 2D textures are required.

Earliest Deadline First Scheduling with Active Buffer Management for Real-Time Traffic in the Internet

We studied the problem of QoS guarantee for differentiated services. A two-level hierarchical scheduling framework was deployed to separate QoS metrics. Due to its desirable property of minimizing the maximum packet lateness, the Earliest Deadline First (EDF) scheduling was adopted to provide the in-class scheduling for the time-sensitive traffic. We employed an EDF scheduler combined with an active buffer management scheme (CHOKe) to improve the fairness of resource allocation and to maintain a good delay performance for real-time applications. Simulation results showed that the proposed scheme can achieve a better delay performance and make a more fair bandwidth allocation between the real-time TCP and UDP connections than the First Come First Served (FCFS) scheduling with the drop-tail buffer management which is commonly deployed in traditional IP routers.

An adaptive fuzzy logic controller: its VLSI architecture and applications

Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The purpose of this paper is to present such an adaptive memory-efficient FLC and its applications. Taking advantage of the adaptability provided by a symbolic fuzzy rule format and the dynamic membership function generator, as well as the high-speed integration capability afforded by VLSI, the proposed adaptive fuzzy logic controller (AFLC) can perform an adaptive fuzzy inference process using various inference parameters, such as the shape and location of a membership function, dynamically and quickly. Three examples are used to illustrate its applications, and the experimental results show the excellent adaptability provided by AFLC.

Determining update latency bounds in Galactica Net

The paper looks at the problem of ensuring the performance of real-time applications hosted on Galactica Net, a mesh-based distributed cache coherent shared memory multiprocessing system. A method for determining strict upper bounds on worst case latencies in wormhole routed networks of known or unknown communication patterns is presented. From this, a tool for determining upper bounds for shared memory update latencies is developed, and it is shown that the update latency of Galactica Net is deterministic. The analytical bounds are then compared with maximum latencies observed in simulations of GNet, with which they compare favorably. Finally, it is shown that the tool for determining update latency bounds is useful for comparing differing GNet system configurations in order to minimize update latency bounds.