Processor Performance Research Articles

Provable bounds for noise-free expectation values computed from noisy samples.

Quantum computing has emerged as a powerful computational paradigm capable of solving problems beyond the reach of classical computers. However, today's quantum computers are noisy, posing challenges to obtaining accurate results. Here, we explore the impact of noise on quantum computing, focusing on the challenges in sampling bit strings from noisy quantum computers and the implications for optimization and machine learning. We formally quantify the sampling overhead to extract good samples from noisy quantum computers and relate it to the layer fidelity, a metric to determine the performance of noisy quantum processors. Further, we show how this allows us to use the conditional value at risk of noisy samples to determine provable bounds on noise-free expectation values. We discuss how to leverage these bounds for different algorithms and demonstrate our findings through experiments on real quantum computers involving up to 127 qubits. The results show strong alignment with theoretical predictions.

Comparing Performance in the Codes AREPO, GIZMO and GAMER-2

Modern astrophysical simulation is the main aspect of human getting insight from the cosmos. Numerical simulations became irreplaceable tools for generating various phases of the universe, the formation of galaxies, and other astrophysical phenomena. As the advances of computational power, validity and diversity of astrophysical modeling have been growing. In addition to the development of the processor performance, the diversity of the software community is also rising therefore, research between various simulation codes is worthwhile. It allowed researchers to know the nature of different simulation techniques linked to their basic algorithms. This study summarizes the basics of common simulation methods used by researchers including N-body Simulations, Smoothed Particle Hydrodynamics, Monte Carlo Methods, Finite Difference and Finite Element Methods. Furthermore, this research analyzes the basics of AREPO, GIZMO, and GAMER-2 codes, and compared the performance of these codes. Last, according to the analysis, this study discusses and demonstrates the advantages and limitations of these codes. These results shed light on guiding further exploration of cosmology simulations.

Total quality management practices among women shea processors: Implication for job performance and household expenditure

Total Quality Management (TQM) is a strategic framework for the continuous improvement of an organisation's practices to achieve overall performance. In the food industry, TQM practices remain inevitable as far as quality remains a benchmark for sustained competition and customer satisfaction. Small businesses like shea processing require continuous improvement, value addition and quality assurance to guarantee access to lucrative and international markets. This could be realised through TQM implementation. However, there is a dearth of studies on the relevance of TQM practices on the performance of shea processors in the literature particularly in the Ghanaian context. Therefore, this study explored TQM implementation and its impact on small-scale women shea processors which is rare in the literature but of utmost importance. Cross-sectional data were obtained from 120 shea processors using a multi-stage sampling. The Seemingly Unrelated regression and Structural Equation Modelling were used to analyse the data. The study revealed that socioeconomic characteristics (age, education, experience, off-farm job, paid labour), sources of shea nut characteristics (self-collect, value of shea nut collected/purchased) and sales outlet characteristics (big processors) had heterogenous effect on the implementation of various TQM practices. Positively, all the TQM practices had covariance relationships. Further, the implementation of TQM practices such as training and development, innovation and customer focus had diverse positive effects on the number of customers and workers employed, while the number of customers per production had a positive effect on the household expenditure of processors.

Diagnosing quantum crosstalk in superconducting quantum chips by using out-of-time-order correlators

Abstract Performance of a scalable quantum processor critically relies on minimizing crosstalk and unwanted interactions within the system, as it is vital for parallel controlled operations on qubits. We present a protocol not only to provide information about residual coupling but also to effectively discriminate it from the influence of classical crosstalk. Our approach utilizes out-of-time-order correlators (OTOCs) as a signal of quantum crosstalk, making it applicable to various coupling forms and scalable architectures. To demonstrate the effectiveness of our protocol, we provide a theoretical analysis and simulate its implementation in coupled superconducting qubits.

Implementation of Application Specific Instruction set Processor for Approximate Computing

The performance, energy efficiency, power dissipation, and cost of the processors used in Internet of Things edge devices can be improved by introducing approximate computing. In this paper, the design and synthesis of an application-specific instruction set processor for approximate computing is proposed. Approximate computing can also be defined by using Artificial Intelligence-based technique like the Fractal theory and Inconsistent Information System. Application Specific Instruction Set Processor is a new processor design area and is used to design a new instruction set using existing processor configuration available on the EDA tool. From the results, it is observed that significant improvement is achieved in processor performance using the TIE application as compared to without the TIE application which is applied to user-designed instruction.

Stakeholder Knowledge Transfer and Performance of Milk Processors in Nyeri and Laikipia Counties, Kenya

In stakeholder management, knowledge transfer is crucial as it facilitates mutual understanding, ensures that stakeholders are well-informed, and aligns expectations, thereby enhancing collaboration and decision-making processes. This study sought to assess the effect of knowledge transfer among stakeholders on performance of milk processors in Nyeri and Laikipia Counties in Kenya. The target population was the 22 milk processing firms in Nyeri and Laikipia Counties. The respondents to the study were the management staff of milk processing firms, farmers, transporters, marketers, and representatives of the regulators. Data was collected using self-administered structured questionnaires and data was analysed descriptively with the aid of a statistical package for social science software and presented using frequencies and percentages. Results showed an average implementation of knowledge transfer among stakeholders. Correlation analysis was also conducted. The results indicated a significant positive correlation between knowledge transfer and performance, r(564) = .611, p < .001. The study concluded that knowledge transfer among stakeholders significantly influenced performance of milk processors in Nyeri and Laikipia Counties, Kenya. The study underscores the importance of promoting stakeholder engagement practices such as knowledge transfer. Policies that incentivize knowledge transfer programs can be instrumental in enhancing overall industry performance. Milk processors therefore ought to enhance knowledge transfer, especially on quality feeds, artificial insemination, and other inputs as this has a direct impact on the quality of milk and therefore the performance of the processors.

Performance Analysis of Open Source Cloud Computing Architectures

Organizations prioritize cloud computing as the primary solution for ensuring secure and, most importantly, uninterrupted delivery of data. In today's landscape, there are various architectural frameworks offering cloud computing infrastructures to choose from. It is crucial to understand how advantageous the performance offered by a chosen architecture is when making a selection. This study aims to comprehend how effective open-source cloud computing architectures are in specific usage scenarios, provide a comparative perspective, and assist organizations in making informed decisions when selecting their IT infrastructures. In line with the study's objectives, the network, disk, and processor performances of OpenStack, OpenNebula, and Apache CloudStack architectures on the same hardware are examined based on data-driven methods. The Iperf3 tool is used for network performance measurement, the dd (Linux) tool for disk performance measurement, and the Sysbench tool for processor performance measurement. After conducting performance measurements with these tools, it was observed that the OpenNebula architecture outperformed the other architectures in terms of overall performance.

Charge-parity switching effects and optimisation of transmon-qubit design parameters

Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we also analyze the effect of a charge-parity switch caused by quasiparticles on a two-qubit gate. Due to the utilization of the second excited state of a transmon, where the charge dispersion is significantly larger, a charge-parity switch will affect the conditional phase of the two-qubit gate. We derive an analytical expression for the infidelity of a diabatic controlled-Z gate and see effects of similar magnitude in adiabatic controlled-phase gates in the tunable coupler architecture. Moreover, we show that the effect of a charge-parity switch can be the dominant quasiparticle-related error source of a two-qubit gate. We also demonstrate that charge-parity switches induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Furthermore, we introduce a performance metric for quantum circuit execution, encompassing the fidelity and number of single- and two-qubit gates in an algorithm, as well as the state preparation fidelity. This comprehensive metric, coupled with a detailed noise model, enables us to determine an optimal range for the qubit design parameters, as confirmed by numerical simulation. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.

Lean Inventory Management and Performance of Milk Processors in Kenya

Dairy is a key contributor to the Kenyan economy and it helps in poverty alleviation and food nutrition in rural and urban areas. Dairy processing acts as a link between dairy farmers and the consumers in Kenya. However, milk processors have been facing numerous challenges that consequently affect their performance. Poor quality of milk, post-harvest losses resulting from inadequate cooling plants and seasonality of milk production in the country are among the problems the milk processors face. Raw milk, the main inventory for milk processors, is highly perishable and requires processing immediately after collection. However, this has not been the case. In fact, 54% of the invested capacities of milk processors remain underutilized. This calls for leanness in inventory that will ultimately reduce waste and improve firms’ performance through reduced complaints. This study was guided by resource orchestration and lean theory. The study was a census and the unit of analysis was all milk processors in Kenya licensed by the Kenya Dairy Board. A pilot study was conducted to enhance the questionnaire’s quality. A Cronbach Alpha of 0.8 was used. Before the regression was run, diagnostic tests were conducted to check for assumptions of linearity. An analysis of variance was conducted to test the variables’ significance and, ultimately, a multiple regression analysis was run. Maintain zero inventory and use of technology to order inventory and maintain zero inventory had positive and significant coefficients while collaboration with suppliers and members in a supply chain had a negative insignificant coefficient. The study concludes that zero inventory and use of technology to order have significant positive correlation coefficients. This implies that the two can help a firm reduce customer complaints and in return improve performance.

First Impressions of the Sapphire Rapids Processor with HBM for Scientific Workloads

The landscape of high performance computing (HPC) has witnessed exponential growth in processor diversity, architectural complexity, and performance scalability. With an ever-increasing demand for faster and more efficient computing solutions to address an array of scientific, engineering, and societal challenges, the selection of processors for specific applications becomes paramount. Achieving optimal performance requires a deep understanding of how diverse processors interact with diverse workloads, making benchmarking a fundamental practice in the field of HPC. Here, we present preliminary results observed over such benchmarks and applications and a comparison of Intel Sapphire Rapids and Skylake-X, AMD Milan, and Fujitsu A64FX processors in terms of runtime performance, memory bandwidth utilization, and energy consumption. The examples focus specifically on the Sapphire Rapids processor with and without high-bandwidth memory (HBM). An additional case study reports the performance gains from using Intel’s Advanced Matrix Extensions (AMX) instructions, and how they along with HBM can be leveraged to accelerate AI workloads. These initial results aim to give a rough comparison of the processors rather than a detailed analysis and should prove timely and relevant for researchers who may be interested in using Sapphire Rapids for their scientific workloads.

Hardware Compression Method for On-Chip and Interprocessor Networks with Wide Channels and Wormhole Flow Control Policy

Increasing the number of processing cores is currently a common way to boost processor performance. However, the load on the memory subsystem consequently increases as the number of its agents grows. Hardware data compression is an unconventional approach to improving memory subsystem performance by reducing, firstly, the main memory access rate by increasing the cache capacity and, secondly, data traffic by packing the data more densely. The paper describes the implementation of hardware data compression in the on-chip network and interprocessor links of a configuration with wide data transmission channels and a wormhole flow control policy. The existing solutions cannot be applied to such configurations because they are essentially based on using narrow data channels and flow control policies implying uninterrupted packet transmission, which is not maintained with the wormhole flow control. The method proposed in this paper enables the use of hardware compression in the aforementioned configuration by moving data compression and decompression from networks to the connected devices, as well as by using a number of optimizations to hide the data processing delays. Optimizations of some specific cases, such as the transmission of large data packets with several cache lines or the transmission of zero data, are considered. Special attention is given to data transmission via interprocessor links, where, due to their lower bandwidth compared to the on-chip network, data compression can be the most beneficial. The increase in memory subsystem bandwidth from using hardware data compression was confirmed in the experiments showing the relative IPC increase in SPEC CPU2017 benchmarks up to 14 percent.

HBPB, applying reuse distance to improve cache efficiency proactively

Cache memories play a significant role in the performance, area, and energy consumption of modern processors, and this impact is expected to grow as on-die memories become larger. While caches are highly effective for cache-friendly access patterns, they introduce unnecessary delays and energy wastage when they fail to serve the required data. Hence, cache bypassing techniques have been proposed to optimize the latency of cache-unfriendly memory accesses. In this scenario, we discuss HBPB, a history-based preemptive bypassing technique that accelerates cache-unfriendly access through the reduced latency of bypassing the caches. By extensively evaluating different real-world applications and hardware cache configurations, we show that HBPB yields energy reductions of up to 75% and performance improvements of up to 50% compared to a version that does not apply cache bypassing. More importantly, we demonstrate that HBPB does not affect the performance of applications with cache-friendly access patterns.

ExTern: Boosting RISC-V core performance using ternary encoding

This paper presents an effective μ-architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time O(1), into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

Instruction Level Parallelism and Memory Synchronization

The simultaneous or parallel execution of a series of instructions within a computer program is known as instruction-level parallelism, or ILP. ILP stands for the average number of instructions executed throughout each stage of this parallel execution, to be more precise. The architecture known as instruction level parallelism (ILP) allows for the execution of several operations in parallel within a single process, each with its own set of resources, including address space, registers, identifiers, state, and program counters. It describes compiler design strategies and processors intended to carry out operations in parallel to increase processor performance, such as memory load and store, integer addition, and float multiplication.

High area efficiency binary neural processing elements with time-domain signals using SFQ circuits

With the increasing processor performance requirements of convolutional neural networks, we believe that research on superconducting neural networks based on single flux quantum (SFQ) circuits holds significant potential. However, the typical multiply and accumulate operations used in neural networks often lead to a significant increase in circuit area due to the limitations of the integration density of the current SFQ circuit fabrication process. In this work, we propose a binary neural processing element (PE) that utilizes time-domain signal expression. Time-domain signals express multi-bit binary data in time information, which reduces the number of data lines to decrease the circuit area. In the proposed binary neural PE, multiplication is achieved through exclusive-NOR gates and addition is realized by controlling the delay of time-domain signals. We designed and simulated a 3 × 3 convolution circuit using 10 Nb layer process with a critical current density of 10 kA cm−2. Compared to the convolution circuit implemented using conventional SFQ logic, the proposed circuit reduces the number of Josephson junctions by approximately 56% and decreases the area by about 60%.

Quantum circuit distillation and compression

Quantum coherence in a qubit is vulnerable to environmental noise. When long quantum calculation is run on a quantum processor without error correction, the noise causes fatal errors and messes up the calculation. Here, we propose quantum-circuit distillation to generate quantum circuits that are short but have enough functions to produce an output similar to that of the original circuits. The distilled circuits are less sensitive to the noise and can complete calculation before the quantum coherence is broken. We created a quantum-circuit distillator by building a reinforcement learning model, and applied it to the inverse quantum Fourier transform (IQFT) and Shor’s quantum prime factorization. The obtained distilled circuit allows correct calculation on IBM-Quantum processors. By working with the distillator, we also found a general rule to generate quantum circuits approximating the general n-qubit IQFTs. The quantum-circuit distillator offers a new approach to improve performance of noisy quantum processors.

Simple-based Dynamic Decentralized Community Detection Algorithm in socially aware networks

This paper introduces a novel, Simple-based Dynamic Decentralized Community Detection Algorithm (S-DCDA) for Socially Aware Networks. This algorithm aims to address the resource-intensive nature, instabilities and inaccuracies of traditional distributed community detection algorithms. The dynamics of decentralization is evident in the threefold nature of the algorithm: (i) each node of the community is the core of the entire network or community for a certain period of time dependent on their need, (ii) nodes are not centralized around themselves, requiring the consent of the other node to join a community, and (iii) Communities start from a single node to form an initial scale community, the number of nodes and the relationship among them are constantly changing. The algorithm requires low processor performance and memory capacity size of each node, to a certain extent, effectively improve the accuracy and stability of community detection and maintenance. Experimental results demonstrate that in comparison to classical and classical-based improved community detection algorithms, S-DCDA yields superior detection results.

An Overview of the Application of Convolutional Neural Networks inSentiment Analysis

The field of natural language processing, or NLP, uses its understanding of human language to find practical solutions to issues. It mainly includes two parts: the core task and the application. The core task represents the common problem that needs to be solved in various natural language application directions. It includes language models, morphology, grammar analysis, semantic analysis, etc. At the same time, the application section focuses on specific natural language processing tasks such as machine translation, information retrieval, question-answering systems, dialogue systems, etc. Natural language processing has made a significant contribution to the development of human society and the economy and provides strong support for all aspects of research work. Opinion mining, or sentiment analysis, is a subfield of natural language processing that develops systems for identifying and extracting ideas from text. Sentiment analysis is a hot topic since it has many practical applications. Many opinion-expressing texts are available on review sites, forums, blogs, and social media as the amount of publicly available information on the Internet grows. This unstructured information can then be automatically transformed into structured data about products, services, brands, politics, or other topics on which people can express their opinions using sentiment analysis systems. This information can be used for marketing analytics, public relations, product reviews, network sponsor ratings, product feedback, and customer service. With the rapid growth of labeled sample data sets and the notable enhancement in graphics processor (GPU) performance, convolutional neural network research has advanced rapidly and achieved remarkable leads to various computer vision tasks. By reviewing the application of CNN, we see that convolutional operations are naturally suitable for some text processing and, thus, naturally suitable for the background of sentiment analysis.

Validation of satellite-derived water-leaving reflectance in contrasted French coastal waters based on HYPERNETS field measurements

Since 2021, two autonomous HYPERNETS (A new hyperspectral radiometer integrated in automated networks of water and land bidirectional reflectance measurements for satellite validation) stations are operated in contrasted French coastal waters: one in the center of an optically complex coastal lagoon and one at the mouth of a highly turbid estuary. These stations perform predefined sequences of above-water hyperspectral radiometric measurements following a strict viewing geometry. The data recorded by the ®HYPSTAR radiometer is automatically transmitted to servers for quality-controls then computation of the water-leaving reflectance signal. Numerous matchups were identified with high (Sentinel2-MSI and Landsat8/9-OLI) and medium (Sentinel3-OLCI and Aqua-MODIS) spatial resolution satellite data and are analyzed to assess the performance of different atmospheric correction algorithms (Sen2Cor, ACOLITE, POLYMER, iCOR, C2RCC, GRS, BPAC, NIR-SWIR). Considering the specifications of each site (i.e., spatial and temporal variations of water optical properties), optimized matchup protocols are first established to guaranty high quality comparisons between satellite products and field measurements. The matchup results highlight the failure and limits of several atmospheric correction algorithms in complex/turbid coastal waters. The importance of accurate sun glint corrections in low to moderately-turbid waters (with the good performances of POLYMER, C2RCC and GRS processors, e.g., errors (MAPE) lower than 25% in the green spectral region) is also shown while the use of dark targets and spectral fitting to estimate the aerosol contributions is proved to be the most accurate method in the case of turbid waters (with Sen2Cor and ACOLITE errors (MAPE) lower than 20% in the visible and near-infrared spectral regions).