Performance Of Field Programmable Gate Arrays Research Articles

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters.

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications.

Turbo encoder and decoder chip design and FPGA device analysis for communication system

<p>Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.</p>

A systematic literature review on hardware implementation of image processing

Image processing has become under the spotlight recently and leads to a significant shift in various fields such as biomedical, satellite images, and graphical applications. Nevertheless, the poor quality of an image is one of the noticeable limitations of image processing as it restricts efficient data extraction to be conducted. Conventionally, the image was processed via software applications such as MATLAB. In spite of the software's ability to cater to the data extraction of low-quality image issues, it still suffers from the time-consuming issue. As the ability to obtain a rapid outcome is a favorable feature of efficient image processing, the use of hardware in image processing is deemed to keep the addressed issue at bay. Thus, the image enhancement techniques using hardware have gradually rising interest among researchers with numerous approaches such as field programmable gate array (FPGA). In this study, 25 different research papers published from 2016 to 2021 are studied and analyzed to focus on the performance of FPGA as hardware implementation in image processing techniques.

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process.

Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

FPGA implementation of digital 3-D image skeletonization algorithm for shape matching applications

ABSTRACT Image skeletonisation plays an important role in applications such as object identification, object’s shape description, pattern recognition, computer vision, telemedicine, and image compression. In this paper, an architecture is developed for the extraction of a skeleton for the 3-D greyscale object. The algorithm used in this paper is an extension of the 2-D greyscale skeletonisation algorithm presented in the literature. The skeleton of a 3-D greyscale object is extracted by using the boundary peeling off method. The skeletonisation algorithms are computationally intensive and difficult to achieve requirements in real-time. Field Programmable Gate Arrays (FPGAs) are selected for implementation so the real-time requirements are met. The proposed architecture is implemented on Virtex-5 FPGA and tested for an 8 × 8 x 3 greyscale object. Resource utilisation of FPGA and timing performance are investigated and are encouraging.

Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Time-domain back-projection (BP) is a widely known method used in synthetic aperture radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, field-programmable gate array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This article presents a new fixed-point based BP (FxBP) design for FPGA devices and a floating-point-based BP (FlBP) design to compare performance. Both designs are developed with N -dimensional range (NDR) structure and single-work item (SWI) structure using OpenCL. The FPGA performance is evaluated using an FPGA performance metric. It is shown that FxBP-NDR and FxBP-SWI designs generate high-quality back-projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.

A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system

The rapid growing impact of light weight applications (RFID tags, smartcards, sensor nodes and FGPAs) makes security a major concern in communication systems. Light weight cryptographic algorithm or ciphers can provide security and confidentiality of data or messages transmitted. In this paper, we proposed low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system (XTEA-LCS method) to improve the efficiency of encryption and decryption process. The key is the major concern of the encryption and decryption process. So in this research random numbers generated using LCS was used for key purpose, which efficiently reduced area and execution time of XTEA-LCS method and improved the system security. The XTEA-LCS method has been implemented in the Xilinx tool using Verilog code on different Virtex devices such as Virtex6, Low Power Virtex-6 (LP Virtex-6), and Virtex-7. In the field programmable gate array (FPGA) implementation, the number of look up tables (LUTs), slices and flip flops reduced and the frequency increased compared to the existing methods: QTL algorithm, DROM-CSLA-QTL and XTEA. The XTEA-LCS methodology improves the FPGA performances by reducing LUTs by 82.96% and slices by 74.28% than conventional XTEA method.

Bladder Volume Monitoring Using Electrical Impedance Tomography With Simultaneous Multi-Tone Tissue Stimulation and DFT-Based Impedance Calculation Inside an FPGA.

In this article, a novel method for measuring the volume of the urinary bladder non-invasively is presented that relies on the principles dictated by Electrical Impedance Tomography (EIT). The electronic prototype responsible for injecting innocuous electrical currents to the lower abdominal region and measuring the developed voltage levels is fully described, as well as the computational models for resolution of the so-called Forward and Inverse Problems in Imaging. The simultaneous multi-tone injection of current provided by a high performance Field Programmable Gate Array (FPGA), combined with impedance estimation by the Discrete Fourier Transform (DFT) constitutes a novelty in Urodynamics with potential to monitor continuously the intravesical volume of patients in a much faster and comfortable way than traditional transurethral catheterization methods. The resolution of the Inverse Problem is performed by the Gauss-Newton method with Laplacian regularization, allowing to obtain a sectional representation of the volume of urine encompassed by the bladder and surrounding body tissues. Experimentation has been carried out with synthetic phantoms and human subjects with results showing a good correlation between the levels of abdominal admittivity acquired by the EIT system and the volume of ingested water.

Implementation of Dual Stage Multi-rate Filter

In this work, an effort is made towards the design and implementation of dual stage multi-rate digital filter architecture which is suitable for digital receivers and satellite applications with reduced VLSI cost function. The proposed dual stage decimation filter architecture consists of Higher Order Filter (HDF) as first section. To remove the droops created by the HDF section in the pass band and to get the smooth pass band frequency response characteristics, HDF filter is followed by a Corrector/Compensating Finite Impulse Response (FIR) filter network. The compensating FIR is designed using conventional Multiplier and Accumulator (MAC) unit. Initially, the filter architectures frequency response are obtained as per the given specifications using MATLAB. Then, Field Programmable Gate Array (FPGA) based performance metrics are captured and analyzed with respect to area, dynamic power dissipation, delay and power delay product. Based on the FPGA performance metrics, it is observed that the proposed dual stage filter leads to 22% of area saving and 9.5 % reduction in dynamic power dissipation. Mainly these filters are best suited for Digital Signal Processing applications in wireless receivers.

Low Power FPGA Implementation of Multi-View Video Coding with Hybrid Compression and Decompression Algorithm

The video is one of the most useful and most appealing medium to represent some information. More usage of digital multi-media via communications media, wireless communications, intranet, internet and cellular mobile leads to the uncontrollable growth of data in media. The video compression technique is used in this research work to improve the processing speed of the entire system. In this work, Low Cost - Multi Video Coding - Hybrid Compression and Decompression (LC-MVC-HCD) method is used to reduce computation complexity. The combinational of Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) algorithms are denoted as hybrid algorithm. Based on this hybrid algorithm, the compression process is performing which improves the video coding efficiency of MVC. The LC-MVC-HCD methodwas implemented in the Matlab, Xilinx and Cadence tool. In Application Specific Integrated Circuit (ASIC) implementation, the area, power, and delay minimized by using the cadence encounter tool with 180nm and 45nm technology. In Field Programmable Gate Array (FPGA) implementation, the number of Lookup Tables (LUTs), slice, and flip-flop are minimized based on two different kinds of Virtex devices such as Virtex -6 and Virtex-7. In Matlab, Peak Signal to Noise Ratio (PSNR), computational time and bit error rate were analyzed for the LC-MVC-HCD method. The experimental outcome showed that the proposed methodology has improved performance ASIC and FPGA up to 2-3% compared to existing methods like Direct mode decision MVC and LC-MVC-DWT.

Low-Power Dynamic Object Detection and Classification With Freely Moving Event Cameras.

We present the first purely event-based, energy-efficient approach for dynamic object detection and categorization with a freely moving event camera. Compared to traditional cameras, event-based object recognition systems are considerably behind in terms of accuracy and algorithmic maturity. To this end, this paper presents an event-based feature extraction method devised by accumulating local activity across the image frame and then applying principal component analysis (PCA) to the normalized neighborhood region. Subsequently, we propose a backtracking-free k-d tree mechanism for efficient feature matching by taking advantage of the low-dimensionality of the feature representation. Additionally, the proposed k-d tree mechanism allows for feature selection to obtain a lower-dimensional object representation when hardware resources are limited to implement PCA. Consequently, the proposed system can be realized on a field-programmable gate array (FPGA) device leading to high performance over resource ratio. The proposed system is tested on real-world event-based datasets for object categorization, showing superior classification performance compared to state-of-the-art algorithms. Additionally, we verified the real-time FPGA performance of the proposed object detection method, trained with limited data as opposed to deep learning methods, under a closed-loop aerial vehicle flight mode. We also compare the proposed object categorization framework to pre-trained convolutional neural networks using transfer learning and highlight the drawbacks of using frame-based sensors under dynamic camera motion. Finally, we provide critical insights about the feature extraction method and the classification parameters on the system performance, which aids in understanding the framework to suit various low-power (less than a few watts) application scenarios.

A novel magnetic island structure identification system based on Mirnov probes and DDR3 look-up table for HL-2A tokamak

A novel magnetic island structure identification (MISI) system based on Mirnov probes and DDR3 look-up table has been developed on the HL-2A device. The system is dedicated to identify the magnetic island by analyzing the measurement of Mirnov probes and equilibrium fitting (EFIT) code. The applications of high-precision sampling and PCI express (PCIe) platform in the system provides the convenience for Mirnov measurements and the EFIT results transmission. A high performance field programmable gate array (FPGA) is used to realize the real-time identification algorithm. By applying the DDR3 look-up table, 30 current filaments are arranged on a 129× 129 grid in the calculation of perturbation flux, simplifying the algorithm structure and improving the efficiency. For the advantage of parallel and pipeline processing abilities in the FPGA, the magnetic island structure can be identified with time resolution of 3 ms and spatial resolution of 1.37 cm and 1.02 cm.

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

In recent years, Fast Fourier Transform (FFT) plays a vital role in signal processing application for converting time domain to frequency domain. This paper presents Real FFT architecture which is implemented in radix-2 Decimation- in-Frequency (DIF). Instead of using more number of Random Access Memory (RAM), single Dual port RAM (DRAM) is used to store the intermediate data results. In Processing Element (PE), normal multiplier and adder has been used in previous works. In this paper, Vedic Multiplier (VM) and Carry Lookahead Adder (CLA) is used for improving the Real FFT operation and it is implemented in Verilog code. Application Specified Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA) performances are evaluated for all the architectures. In DRAM-VM-CLA architecture, LUT, flip flop, slices, and frequency are improved in FPGA performance as well as area, power, and delay are improved in ASIC performance. In ASIC 180 nm technology, 81.14% of area, 45.98% of delay, and 89.77% of Area Delay Product (ADP) is minimized in DRAM-VM-CLA as well as 72.64% of area, 5.44% of delay, and 74.10% of ADP is reduced in ASIC 45 nm technology.

Adaptive absolute SCORE algorithm for spectrum sensing in cognitive radio

The Cognitive Radio (CR) is one of the significant technology to enhance the spectrum utilization efficiency. The Radio Frequency (RF) spectrum is the most valuable natural resource. Due to an increased usage of the cognitive radio, the sensing issues in spectrum are increasing day by day. The CR is emerging technologies that increase the effectiveness and efficiency of the spread spectrum communication. Generally, the spectrum sensing is based on the energy detection and cyclostationary feature detection. The energy detection is a fundamental basic spectrum sensing technique. However, it performs poorly under a low Signal-to-Noise Ratio (SNR) environment. The cyclostationary based sensing technique improves Primary Users (PUs) detection performance with the high complexity of implementation and hardware utilization. Traditional median and Finite Impulse Response (FIR) filters are utilized complex adder and multiplier, which requires large memory space to store the filter coefficients and more hardware utilization. Hence, these filters have computational complexity and more hardware utilization. To overcome above-mentioned problems, Adaptive Absolute SCORE (AA-SCORE) architecture is designed based on optimal FIR filter for further reducing the system complexity to enhance the spectrum utilization efficiency in CR. In this research, the FIR filter is designed by using Radix-8 and Carry Select Adder (CSLA) for reducing the filter complexity. The proposed method is named as AAS-R8-CSLA architecture. The AAS-R8-CSLA architecture was implemented in the Field Programmable Gate Array (FPGA) platform through Verilog code. In order to improve the spectrum utilization efficiency of CR by using AAS-R8-CSLA. The experimental outcome showed that the proposed AAS-R8-CSLA architecture has improved FPGA performance up to 2–3% compared to existing methods like AAS and ACS architecture.

Estimating and Mitigating Aging Effects in Routing Network of FPGAs

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the stress through the interconnection resources. By observing the impact of the signal probability on the aging of routing buffers, we enhance the synthesis flow as well as augment the proposed routing algorithm to converge the signal probabilities toward aging-friendly values. Experimental results over a set of industrial benchmarks and commerciallike FPGA architecture indicate the effectiveness of the proposed method with 64.3% reduction of stress duration in multiplexers and up to 45.2% improvement of the degradation of buffers. Altogether, the proposed method reduces the timing guardband by from 14.1% to 31.7%, depending on the FPGA routing architecture.

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

Modern field programmable gate arrays (FPGAs) have evolved significantly in recent years and have found applications in various fields like cryptography, defense, aerospace, and many more. The integration of FPGA with highly efficient modules like DSP and block RAMs has increased the performance of FPGA significantly. This paper addresses the lesser explored feature of modern FPGA called as reconfigurable LUT (RLUT) whose content can be updated internally, even during run-time. We describe the basic functionality of RLUT and discuss its potential applications for security from both destructive and constructive point of view, highlighting the conflicted usage of RLUTs. Several use cases exploiting RLUT feature in security-critical scenarios (physical attacks related in particular) are studied in detail. The paper proposes design of stealthy hardware Trojans having zero payload overhead to highlight destructive applications which can be built using hardware Trojans. On the other hand, this paper also highlights several constructive applications based on RLUT features, starting from lightweight side-channel countermeasures to kill switch to prevent the FPGA hardware from environmental hazards and malicious attack attempts.

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA

Due to the conventional look-up-table (LUT) using the static random access memory (SRAM) cell, field programmable gate arrays (FPGAs) almost reach the limitation in term of the density, speed, and configuration overhead. This paper proposes an improved memristor-based LUT (MLUT) circuit which is compatible with the mainstream LUT circuit in FPGA. Any arbitrary combined logic functions can be implemented in the MLUT through specific configurations. Then the MLUT shows superior advantages over the conventional LUT such as smaller area overhead and fewer data transmission. As a case study, a one-bit full adder is simulated to verify that the design is of practice in PSPICE. Moreover, the adder can be cascaded into multibit full adder demonstrating competitiveness against the conventional configurable logic block in FPGA technology. MLUT can be a candidate to replace the conventional SRAM-based LUT and further improves the performance of FPGAs.