Pentacene TFTs Research Articles

Room-temperature solution-processed, ZrOx-based hybrid gate dielectrics for low-voltage organic thin-film transistors on plastic substrates

For advanced electronic device applications including printable, flexible organic electronics and bioelectronics, it is crucial to develop novel dielectric materials with high dielectric strength and low-temperature processability compatible with plastic substrates for producing flexible and low-voltage organic thin-film transistors (OTFTs). Herein, we report the facile fabrication of rationally designed, high-capacitance hybrid gate dielectric films for low-voltage OTFTs on plastic substrates via a room-temperature solution process. To create room-temperature-processed gate dielectrics with high dielectric strength, we designed organic-inorganic hybrid gate dielectric films by including ZrOx networks as inorganic high-k oxide materials for obtaining large capacitance and 1,6-hexanediol diacrylate as a bifunctional UV cross-linking agent and a flexible organic component for increasing the density and flexibility of films and ensuring room-temperature processability. The UV cross-linked ZrOx-based hybrid composite films with a 15 nm thickness showed excellent dielectric properties with a leakage current density of ∼10−6 A/cm2 and a capacitance of 640 nF/cm2. The film surfaces were modified with hydrophobic self-assembled monolayers to match the surface energy of organic semiconductors for enhancing the OTFT performance. The utility of the hybrid dielectrics for flexible OTFTs was demonstrated by realizing pentacene TFTs on plastic substrates with a low operating voltage at –2.5 V, a high on/off current ratio of 105, a threshold voltage as low as –0.7 V, and a hole mobility up to 0.47 cm2 V−1 s−1, which are comparable to those performed on Si substrates.

Solution-processed amorphous ZrO2 gate dielectric films synthesized by a non-hydrolytic sol-gel route.

Solution-processed zirconium oxide (ZrO2) dielectrics were formed via a non-hydrolytic sol–gel route at low-temperature, and are suitable for flexible thin film transistor (TFT) devices. Precursor solutions with equimolar zirconium halide and zirconium alkoxide were prepared, and amorphous ZrO2 films were obtained by spin-coating and annealing at 300 °C through the direct condensation reaction between them. The ZrO2 films exhibited a high dielectric constant near 10, and a low leakage current density of 5 × 10−8 A cm−2 at a field of 1 MV cm−1. High mobility p-type pentacene TFTs were fabricated using the ZrO2 dielectrics, with a saturation field-effect mobility of 3.7 cm2 V−1 s−1, a threshold voltage of −2.7 V, an on/off ratio of 1.1 × 106 and a subthreshold swing of 0.65 V dec−1.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

Patterned water dispersible conducting polymer electrode in organic thin film transistor through a parylene lift-off process

Availability of non-destructive micro-patterning techniques is essential for the realization of organic electronic technologies that are compatible with chemically sensitive materials. Organic thin film transistors (OTFTs) with conductive polymer composite poyaniline:polystyrene sulphonic acid (PANi-PSS) electrodes that are fabricated by a simple modified Parylene lift-off process is reported. The functionality of the conducting and semiconducting material is not affected by this technique and it is fully amenable for patterning on a flexible substrate. This patterning technique for conducting polymer electrode, without exposure to harmful solvents, results in a resolution of 5μm. Water dispersible nanostructured conducting PANi-PSS composite for patterning was synthesized by bulk polymerization of aniline templated with polystyrene sulphonic acid. For the formation of stable dispersion of PANi-PSS with desired conductivity, concentration of the precursor acid used in the synthesis was optimized. The conductivity of films thus obtained from a stable dispersion was increased by more than two orders of magnitude by secondary doping with dichloroacetic acid. Elucidation of the mechanism by which this conductivity improvement occurs was done using Ultraviolet Visible spectroscopy and X-ray diffraction analysis. Morphology characterization of the synthesized nanoparticles and thin films in OTFT was carried out using Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). Electrical characteristics of bottom contact pentacene TFTs with PANi-PSS electrodes and pentacene active material is superior to those with palladium electrodes due to a lower charge injection barrier. Contact resistance was extracted in both the cases by Transfer Line Method (TLM).

Low leakage current through zirconium oxide gate fabricated by low temperature solution process in OTFTs on plastic substrate

Abstract Zirconium oxide (ZrOx) sol-gel solutions have been used as a high dielectric material for the low voltage operation of organic TFTs (OTFTs). However, ZrOx has disadvantages, including a large off-state current greater than 100 pA and a high annealing temperature above 400 °C, which must be resolved before it can be applied to flexible electronics. In this study, a multiple spin-coating process was used to increase the thickness of the ZrOx gate dielectric layer and reduce the large off-state current. The large off-state current of pentacene TFTs was decreased to 1 pA by a ZrOx gate thickness of 70 nm. Notably, the process was performed at a low temperature of 300 °C and thus was applicable to poly carbonate plastic substrates. In addition, low voltage operation (Ion = 6.4 μA at VGS = −5 V) was also achieved with the thick gate of 70 nm. The mobility was in the range of 0.32–0.43 cm2/V s. An unusual positive off-state current region appeared in the transfer characteristics, likely due to acceptor-like states generated at the interface between a pre-deposited and additional ZrOx layer, spin-coated during the multiple coating process.

Bias stress effects in pentacene thin-film transistors with poly(methyl methacrylate) gate insulator

ABSTRACTWe demonstrated a bias stress effect on organic thin-film transistors (OTFTs) that causes device degradation, including a large shift in the threshold voltage and hysteresis in the transfer characteristics. Specifically, we analyzed the electrical characteristic variations in pentacene TFTs with a poly(methyl methacrylate) gate insulator under different bias stress conditions. We found that bias stress between the gate electrode and source/drain electrodes affects the charge transport properties, whereas bias stress between the source and drain electrodes influences the charge injection properties.

A DC current–voltage model for organic thin film transistor for circuit design

Organic integrated circuits based on organic thin film transistors (OTFT) are gaining more and more attention nowadays, the availability of accurate spice-like device model for OTFTs suitable for Electronic design automation (EDA) applications is particularly attractive. In this paper, we demonstrate the applicability of the accurate direct-current (DC) model for OTFTs suitable for EDA, the parameters in the unified model all can be extracted in a simple and direct way from the experimental measurements. Two types of top source and drain contact (TC) pentacene TFTs with different gate dielectrics are researched on, simulation results based Simulation Program with Integrated Circuit Emphasis (SPICE) are obtained with this model and parameters extracted, which show a very good agreement with measured curves in both transfer and output characteristics, so the DC model and the extracted parameters are verified.

A Comparative Investigation of a Pentacene Layer on Gold and PMMA in Bottom-Contact Pentacene Thin Film Transistors

This study demonstrates an attempt to fabricate the 25 µm channel-length bottom-contact pentacene TFTs using thermal evaporation through shadow mask technique and to investigate crystal structure, morphology and electronic structure of the pentacene layer deposited at the same time on gold (Au) source-drain electrodes and Poly(methyl methacrylate) (PMMA) gate-dielectric of the TFTs. The pentacene layers with thicknesses of 50 nm were deposited at the evaporation rates of 0.1, 0.5, 1.0 and 1.5 nm/min at substrate temperatures of 60 °C. These conditions were employed with and without preheating at 80 °C before deposition. Preheating at 80 °C was found to improve quality of the pentacene film on the PMMA gate-dielectric. Using the deposition rate of 1 nm/min and the substrate temperature of 60 °C, best performance of TFTs were obtained. At this deposition condition, pentacene film work function was found to be higher on the Au source-drain electrodes than on the PMMA gate-dielectric.

Carrier Mobility Enhancement in Organic TFTs with Gate Insulator of Vertical Liquid Crystal Alignment Film

In order to improve the carrier mobility of pentacene organic thin-film transistors (O-TFTs), we have studied the effect of the gate insulator material on the mobility. In spite of a reduction of the grain size, a gate insulating polymer material with a low surface energy, which is used for vertical alignment films for liquid crystals, significantly enhances the carrier mobility of the pentacene TFTs from ∼0.4 to up to ∼1.2 cm2 Vs.

Charge Transport Model Based on Single-Layered Grains and Grain Boundaries for Polycrystalline Pentacene Thin-Film Transistors

The charge transport process in organic thin-film transistors (OTFTs) has always been under intensive research while the mechanism is still controversial, even in the small-molecule OTFTs. In this study, we report on a transport model for interpreting the charge transport mechanism in polycrystalline pentacene TFTs. By investigating the growth mode of pentacene films and the distribution of charge carriers in the channel of OTFTs, a transport model involving two-dimensional single-layered grains and grain boundaries (GBs), namely the two-dimensional grain boundary (TDGB) model, is proposed for describing the charge transport process in polycrystalline pentacene TFTs. An analytical expression for the field-effect mobility could be obtained from the model. The model is applied to explain the mobility dependence on the grain sizes at the first monolayer of pentacene films, temperature and on gate voltage in polycrystalline pentacene TFTs, with good agreement obtained. In addition, the values of some crucial parameters are given by the simulations based on the model.

Low-temperature and scalable complementary thin-film technology based on solution-processed metal oxide n-TFTs and pentacene p-TFTs

In this work, a completely scalable integration process is presented for organic–inorganic complementary logic, based on low-temperature spin-coated n-type metal oxide TFTs and thermally evaporated p-type pentacene TFTs. Both transistor types are photolithographically processed side-by-side, without the use of any shadow mask. High performance n-type metal oxide TFTs, post-annealed at a maximum temperature of only 250 °C, exhibit saturation mobilities exceeding 2 cm 2/(V s), subthreshold swing as low as 0.19 V/decade and I on/ I off ratios beyond 10 7 after integration with p-type pentacene TFTs. Using this hybrid complementary technology, 5-stage and 19-stage ring-oscillators are demonstrated, operating at supply voltages as low as 2.5 V. The ring-oscillators oscillate at a frequency of more than 110 kHz, corresponding to stage delays as low as 0.74 μs, at a supply bias of 20 V.

A high-vacuum deposition system for in situ and real-time electrical characterization of organic thin-film transistors

We present a home-built high-vacuum system for performing organic semiconductor thin-film growth and its electrical characterization during deposition (real-time) or after deposition (in situ). Since the environment conditions remain unchanged during the deposition and electrical characterization process, a direct correlation between growth mode and electrical properties of thin film can be obtained. Deposition rate and substrate temperature can be systematically set in the range 0.1-10 ML∕min and RT-150 °C, respectively. The sample-holder configuration allows the simultaneous electrical monitoring of up to five organic thin-film transistors (OTFTs). The OTFTs parameters such as charge carrier mobility μ, threshold voltage V(TH), and the on-off ratio I(on)∕I(off) are studied as a function of the semiconductor thickness, with a submonolayer accuracy. Design, operation, and performance of the setup are detailed. As an example, the in situ and real-time electrical characterization of pentacene TFTs is reported.

Fabrication of 6,13‐bis(triisopropyl‐silylethynyl)–pentacene thin‐film transistors with the silver ink transfer method using a polymer stamp

AbstractWe fabricated 6,13‐bis(triisopropylsilylethynyl)–pentacene (TIPS–pentacene) thin film transistors using a direct metal transfer method. Using different metals, such as Au and Ag ink, electrode patterns are formed from the relief region of the polymer mold. TIPS–pentacene TFTs using the Ag ink transfer method show a similar performance to those using the Au metal transfer method. This method has advantages over the Au metal transfer method because it does not require vacuum equipment and a dry etching process. The self‐assembled monolayer (SAM) treated device exhibits a carrier mobility of 9.5 × 10–2 cm2/V · s, and an on/off ratio of 4.6 × 104. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Influence of structural properties on environmental stability of pentacene thin film transistors

We studied environmental stability of top contact pentacene TFTs with active layer evaporated at different growth rates. We measured the transfer characteristics in vacuum and in air and after storing the devices in oxygen for several days. Different pentacene growth rates result in different grain size of active layer. This morphology difference influences the hysteresis of transfer characteristics induced by water absorption. On the contrary, aging effects on the transfer characteristics of pentacene O-TFTs, induced by oxygen diffusion into the active layer, are not related to structural characteristics of pentacene film.

저온 공정 PVP게이트 절연체를 이용한 고성능 플렉서블 유기박막 트랜지스터의 계면처리 효과

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as , , and of 0.75 V/decade, respectively.

Flexible Pentacene Thin Film Transistors with Cyclo-Olefin Polymer as a Gate Dielectric

Flexible pentacene thin film transistors were fabricated and characterized with a hydroxyl-free and amorphous low-k cyclo-olefin polymer (COP) as a gate dielectric. The maximum processing temperature was 60°C. The spin-coated COP thin films had excellent electrical insulating properties, and the pentacene TFTs showed negligible current hysteresis, a field-effect mobility of 1.60cm2 /Vs, a subthreshold swing of 0.56V/decade and an on/off ratio of>106. Furthermore, a small threshold voltage shift below 1.83V was obtained despite unpassivation of the pentacene layer after a gate bias stress of 104 s. These excellent air stabilities were attributed to the insulator with hydroxyl-free and low water absorbency.

Selective coating of PPE pentacene on TFT region for solution processed organic electronics

We have studied the selective coating on the TFT region by spin-casting of 6,13-bis(4-pentylphenylethynyl) pentacene (PPE pentacene). The island of PPE pentacene was formed inside of the banks for TFT, which was independent of self-assembled monolayer layer on source/drain electrodes. A bottom contact TFT with the PPE pentacene using selective coating on TFT region, exhibited the field-effect mobility of 0.02 cm 2/V s, an on/off current ratio of 10 7 and gate voltage swing of 0.8 V/dec. An inverter made of PPE pentacene TFTs was demonstrated to have the signal gain of >1.5 ( V DD = −40 V) using selective coating.

Fine patterning of glycerol-doped PEDOT:PSS on hydrophobic PVP dielectric with ink jet for source and drain electrode of OTFTs

This report describes the fabrication and the electrical characteristics of pentacene OTFTs that use the conducting PEDOT:PSS for the source and drain (S/D) electrodes. By adding a controlled amount (10–20 wt.%) of glycerol the conductivity of the PEDOT:PSS ink enhanced to 450 S/cm, and the viscosity of the ink was reduced to <20 cps in order for it to be suitable for ink jet printing. In order to create a patterned PEDOT:PSS layer for the S/D electrode on a hydrophobic polyvinylphenol (PVP) gate dielectric, oxygen plasma was applied to control the surface energy of S/D electrode area on the PVP surface. In addition, by adding a leveling agent, the pattern of PEDOT:PSS droplet was improved enough to be spread up to the corners of S/D electrode area, producing channel length of 10 μm with a fine shape. Pentacene TFTs with the PEDOT:PSS S/D electrodes exhibited a similar performance to those with Au S/D electrodes in terms of the electrode resistance, corresponding to sum of the electrode series resistance and the contact resistance, being ∼30 kΩ cm at V G = −25 V and the field effect mobility being 0.13 cm 2/V s and the on/off current ratio being 5.6 × 10 6. However, the electrode resistance of the PEDOT:PSS needs to be further reduced for the short channels <20 μm.

Solution-Prepared Hybrid-Nanoparticle Dielectrics for High-Performance Low-Voltage Organic Thin-Film Transistors

Oleic acid capped barium strontium titanate (OA-BST) nanoparticles were synthesized for solution-prepared dielectrics in organic thin-film transistors (OTFTs). The as-synthesized nanoparticles were well-dispersed in organic solvents to deposit very homogeneous dielectric films by direct spin coating. Bottom-gate pentacene TFTs fabricated using these nanoparticle dielectric films showed high mobilities of 1-2 cm(2) V(-1) s(-1) with on/off ratios of 10(3) under a low driven voltage of -2.5 V. Top-gate poly(3,3'''-didodecylquaterthiophene) (PQT-12) TFTs with nanoparticle dielectrics also exhibited a low-voltage operation (-5 V) performance with mobilities of 0.01-0.1 cm(2) V(-1) s(-1) and on/off ratios of 10(3)-10(4). Detailed studies on the gate voltage-dependent mobility of the devices showed that only a low gate electric field needed to achieve the saturated mobility for the OA-BST-based pentacene OTFTs could be attributed to the low trapped-state densities (<3.9 x 10(11) cm(-2)) at the dielectric/semiconductor interfaces for these devices.

44.1: Introducing a Two Stage Fully Organic AMOLED Display; from Design to Fabrication

AbstractIn this paper, we introduce the design and the fabrication of a fully organic AMOLED display array. for solving the need of large OTFTs' area issue, the pixel structure is designed in a way such that a top‐emitting OLED is stacked on top of the driving circuitry including two pentacene TFTs. The pixel component geometries are designed and selected based on circuit simulation using behavioral SPICE‐like models for pentacene TFTs and OLEDs. Moreover a new method is developed to provide the electronic connection between the OLED and the driving circuit.